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Low-Power Embedded Pentium
Processor with MMX Technology
12
Advance Information Datasheet
The code cache, branch target buffer and prefetch buffers are responsible for getting raw
instructions into the execution units of the Pentium processor. Instructions are fetched from the
code cache or from the external bus. Branch addresses are remembered by the branch target buffer.
The code cache TLB translates linear addresses to physical addresses used by the code cache.
The decode unit decodes the prefetched instructions so the Pentium processor can execute the
instruction. The control ROM contains the microcode which controls the sequence of operations
that must be performed to implement the Pentium processor architecture. The control ROM unit
has direct control over both pipelines.
The Pentium processor contains a pipelined floating-point unit that provides a significant floating-
point performance advantage over previous generations of processors.
In addition to the SMM features described above, the Pentium processor supports clock control.
When the clock to the processor is stopped, power dissipation is virtually eliminated. The
combination of these improvements makes the Pentium processor a good choice for low-power
embedded designs.
The Pentium processor supports fractional bus operation. This allows the internal processor core to
operate at high frequencies, while communicating with the external bus at lower frequencies.
The low-power embedded Pentium processor with MMX technology contains an on-chip advanced
programmable interrupt controller (APIC). This function is reserved for future multi-processing
function.
The architectural features introduced in this section are more fully described in the
Embedded
Pentium
Processor Family Developer’s Manual
(order number 273204).
2.2
Pentium
Processor with MMX Technology
The Pentium processor with MMX technology for high-performance embedded designs is a
significant addition to the Pentium processor family. Available at 166, 200, 233, and 266 MHz, it is
the first microprocessor to support Intel MMX technology.
The Pentium processor with MMX technology is both software and pin compatible with previous
members of the Pentium processor family. It contains 4.5 million transistors and is manufactured
on lntel’s enhanced 0.35 micron (200/233 MHz) or 0.25 micron (166/266 MHz) CMOS process,
which allows voltage reduction technology for low power and high density.
In addition to the architecture described in the previous section for the Pentium processor family,
the Pentium processor with MMX technology has several additional micro-architectural
enhancements, which are described in the next section.
2.2.1
Full Support for Intel MMX Technology
MMX technology is based on the SIMD technique (Single Instruction, Multiple Data) which
enables increased performance on a wide variety of multimedia and communications applications.
Fifty-seven new instructions and four new 64-bit data types are supported in the Pentium processor
with MMX technology. All existing operating system and application software are fully-
compatible.