參數(shù)資料
型號(hào)： Embedded Pentium 266
廠商： Intel Corp.
英文描述： Low-Power Embedded Pentium Processor with MMX Technology(低能量嵌入式帶MMX技術(shù)奔騰處理器)
中文描述： 低功耗嵌入式處理器奔騰MMX技術(shù)（低能量嵌入式帶MMX公司的技術(shù)奔騰處理器）
文件頁(yè)數(shù)： 27/62頁(yè)
文件大?。?/td> 1130K
代理商： EMBEDDED PENTIUM 266
Low-Power Embedded Pentium
Processor with MMX Technology
Advance Information Datasheet
27
PEN#
I
The
parity enable
input (along with CR4.MCE) determines whether a machine
check exception will be taken as a result of a data parity error on a read cycle. If this
pin is sampled active in the clock, a data parity error is detected. The processor will
latch the address and control signals of the cycle with the parity error in the machine
check registers. If, in addition, the machine check enable bit in CR4 is set to “1”, the
processor will vector to the machine check exception before the beginning of the
next instruction.
PICCLK
I
The APIC interrupt controller serial data bus clock is driven into the
programmable
interrupt controller clock
input of the Pentium processor with MMX technology.
PICD0
–
PICD1
[APICEN]
I/O
Programmable interrupt controller data lines 0
–
1
of the Pentium processor with
MMX technology comprise the data portion of the APIC 3-wire bus. They are open-
drain outputs that require external pull-up resistor. These signals are multiplexed
with APICEN.
PM/BP[1:0]
O
These pins function as part of the performance monitoring feature.
The breakpoint 1
–
0 pins are multiplexed with the
performance monitoring 1-0
pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins come
out of RESET configured for performance monitoring.
PRDY
O
The
probe ready
output pin indicates that the processor has stopped normal
execution in response to the R/S# pin going active or Probe Mode being entered.
PWT
O
The
page writethrough
pin reflects the state of the PWT bit in CR3, the page
directory entry, or the page table entry. The PWT pin is used to provide an external
writeback indication on a page-by-page basis.
R/S#
I
The
run/stop
input is provided for use with the Intel debug port. Please refer to the
Embedded Pentium
Processor Family Developer’s Manual
(Order Number
273204) for more details.
RESET
I
RESET
forces the processor to begin execution at a known state. All the processor
internal caches will be invalidated upon the RESET. Modified lines in the data cache
are not written back. FLUSH# and INIT are sampled when RESET transitions from
high to low to determine if three-state test mode will be entered or if BIST will be
run.
SCYC
O
The
split cycle
output is asserted during misaligned LOCKed transfers to indicate
that more than two cycles will be locked together. This signal is defined for locked
cycles only. It is undefined for cycles which are not locked.
SMI#
I
The
system management interrupt
causes a system management interrupt
request to be latched internally. When the latched SMI# is recognized on an
instruction boundary, the processor enters System Management Mode.
SMIACT#
O
An active
system management interrupt active
output indicates that the
processor is operating in System Management Mode.
STPCLK#
I
Assertion of the
stop clock
input signifies a request to stop the internal clock of the
Pentium processor with voltage reduction technology thereby causing the core to
consume less power. When the CPU recognizes STPCLK#, the processor will stop
execution on the next instruction boundary, unless superseded by a higher priority
interrupt, and generate a Stop Grant Acknowledge cycle. When STPCLK# is
asserted, the processor will still respond to external snoop requests.
TCK
I
The
testability clock
input provides the clocking function for the processor
boundary scan in accordance with the IEEE Boundary Scan interface (Standard
1149.1). It is used to clock state information and data into and out of the processor
during boundary scan.
TDI
I
The
test data input
is a serial input for the test logic. TAP instructions and data are
shifted into the processor on the TDI pin on the rising edge of TCK when the TAP
controller is in an appropriate state.
Table 6. Quick Pin Reference (Sheet 5 of 6)
Symbol
Type
Name and Function
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