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參數(shù)資料
| 型號： | Embedded Pentium 266 |
| 廠商： | Intel Corp. |
| 英文描述： | Low-Power Embedded Pentium Processor with MMX Technology(低能量嵌入式帶MMX技術(shù)奔騰處理器) |
| 中文描述： | 低功耗嵌入式處理器奔騰MMX技術(shù)（低能量嵌入式帶MMX公司的技術(shù)奔騰處理器） |
| 文件頁數(shù)： | 44/62頁 |
| 文件大?。?/td> | 1130K |
| 代理商： | EMBEDDED PENTIUM 266 |
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Low-Power Embedded Pentium
Processor with MMX Technology
44
Advance Information Datasheet
Table 21. Power Dissipation Requirements for Thermal Design
Parameter
Typical
(1)
Max
(2)
Unit
Frequency
Thermal Design Power
4.1 (HL-PBGA)
4.5 (PPGA)
7.6
Watts
Watts
Watts
166 MHz
166 MHz
266 MHz
Active Power
(3)
2.9
4.5
Watts
Watts
166 MHz
266 MHz
Stop Grant/Auto Halt Powerdown Power
Dissipation
(4)
0.70
0.70
Watts
Watts
166 MHz
266 MHz
Stop Clock Power
(5)
0.06
0.06
Watts
Watts
166 MHz
266 MHz
NOTES:
1. This is the typical power dissipation in a system. This value is expected to be the average value that will be
measured in a system using a typical device at the specified voltage running typical applications. This value
is dependent upon the specific system configuration. Typical power specifications are not tested.
2. Systems must be designed to thermally dissipate the maximum thermal design power unless the system
uses thermal feedback to limit processor’s maximum power. The maximum thermal design power is
determined using a worst-case instruction mix and also takes into account the thermal time constant of the
package.
3. Active power is the average power measured in a system using a typical device running typical applications
under normal operating conditions at nominal V
and room temperature.
4. Stop Grant/Auto Halt Powerdown Power Dissipation is determined by asserting the STPCLK# pin or
executing the HALT instruction. When in this mode, the processor has a new feature which allows it to
power down additional circuitry to enable lower power dissipation. This is the power without snooping at the
specified voltage and with TR12 bit 21 set. In order to enable this feature, TR12 bit 21 must be set to 1 (the
default is 0 or disabled). Stop grant/Auto Halt Powerdown power dissipation without TR12 bit 21 set may be
higher. The Max rating may be changed in future specification updates.
5. Stop Clock Power Dissipation is determined by asserting the STPCLK# pin and then removing the external
CLK input. This is specified at a T
CASE
of 50 °C.
Table 22. Input and Output Characteristics
Symbol
Parameter
Min
Max
Unit
Notes
C
IN
Input Capacitance
15
pF
(4)
C
O
Output Capacitance
20
pF
(4)
C
I/O
I/O Capacitance
25
pF
(4)
C
CLK
CLK Input Capacitance
15
pF
(4)
C
TIN
Test Input Capacitance
15
pF
(4)
C
TOUT
Test Output Capacitance
20
pF
(4)
C
TCK
Test Clock Capacitance
15
pF
(4)
I
LI
Input Leakage Current
±
15
μA
0<V
IN
<V
IL
, V
IH
< V
IN
<V
CC3
,
(1)
I
LO
Output Leakage Current
±
15
μA
0<V
IN
<V
IL
, V
IH
< V
IN
<V
CC3
,
(1)
I
IH
Input High Leakage Current
200
μA
V
IN
= V
CC3
–
0.4 V, (3)
I
IL
Input Low Leakage Current
400
μA
V
IN
= 0.4 V (2, 5)
NOTES:
1. This parameter is for inputs/outputs without an internal pull up or pull down.
2. This parameter is for inputs with an internal pull up.
3. This parameter is for inputs with an internal pull down.
4. Guaranteed by design.
5. This specification applies to the HITM# pin when it is driven as an input (e.g., in JTAG mode).
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