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參數(shù)資料
| 型號： | Embedded Pentium 266 |
| 廠商： | Intel Corp. |
| 英文描述： | Low-Power Embedded Pentium Processor with MMX Technology(低能量嵌入式帶MMX技術(shù)奔騰處理器) |
| 中文描述： | 低功耗嵌入式處理器奔騰MMX技術(shù)（低能量嵌入式帶MMX公司的技術(shù)奔騰處理器） |
| 文件頁數(shù)： | 24/62頁 |
| 文件大?。?/td> | 1130K |
| 代理商： | EMBEDDED PENTIUM 266 |
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Low-Power Embedded Pentium
Processor with MMX Technology
24
Advance Information Datasheet
BF2–BF0
I
The
Bus Frequency
pins determine the bus-to-core frequency ratio. BF [2:0] are
sampled at RESET, and cannot be changed until another non-warm (1 ms)
assertion of RESET. Additionally, BF[2:0] must not change values while RESET is
active. See Table 7 for Bus Frequency Selection.
In order to override the internal defaults and guarantee that the BF[2:0] inputs
remain stable while RESET is active, these pins should be strapped directly to or
through a pullup/pulldown resistor to V
or ground. Driving these pins with active
logic is not recommended unless stability during RESET can be guaranteed.
During power up, RESET should be asserted prior to or ramped simultaneously with
the core voltage supply to the processor.
BOFF#
I
The
backoff
input is used to abort all outstanding bus cycles that have not yet
completed. In response to BOFF#, the processor will float all pins normally floated
during bus hold in the next clock. The processor remains in bus hold until BOFF# is
negated, at which time the processor restarts the aborted bus cycle(s) in their
entirety.
[APICEN]
PICD1
I
Advanced Programmable Interrupt Controller Enable
enables or disables the
on-chip APIC interrupt controller. If sampled high at the falling edge of RESET, the
APIC is enabled. APICEN shares a pin with the PICD1 signal.
BP3–BP2
PM/BP1–BP0
O
The
breakpoint
pins (BP3
–
0) correspond to the debug registers, DR3
–
DR0. These
pins externally indicate a breakpoint match when the debug registers are
programmed to test for breakpoint matches.
BP1 and BP0 are multiplexed with the
performance monitoring
pins (PM1 and
PM0). The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins come
out of RESET configured for performance monitoring.
BRDY#
I
The
burst ready
input indicates that the external system has presented valid data
on the data pins in response to a read or that the external system has accepted the
processor data in response to a write request. This signal is sampled in the T2, T12
and T2P bus states.
BREQ
O
The
bus request
output indicates to the external system that the processor has
internally generated a bus request. This signal is always driven whether or not the
processor is driving its bus.
BUSCHK#
I
The
bus check
input allows the system to signal an unsuccessful completion of a
bus cycle. If this pin is sampled active, the processor will latch the address and
control signals in the machine check registers. If, in addition, the MCE bit in CR4 is
set, the processor will vector to the machine check exception.
To assure that BUSCHK# will always be recognized, STPCLK# must be deasserted
any time BUSCHK# is asserted by the system, before the system allows another
external bus cycle. If BUSCHK# is asserted by the system for a snoop cycle while
STPCLK# remains asserted, usually (if MCE=1) the processor will vector to the
exception after STPCLK# is deasserted. But if another snoop to the same line
occurs during STPCLK# assertion, the processor can lose the BUSCHK# request.
CACHE#
O
For processor-initiated cycles, the
cache
pin indicates internal cacheability of the
cycle (if a read), and indicates a burst writeback cycle (if a write). If this pin is driven
inactive during a read cycle, the processor will not cache the returned data,
regardless of the state of the KEN# pin. This pin is also used to determine the cycle
length (number of transfers in the cycle).
CLK
I
The
clock
input provides the fundamental timing for the processor. Its frequency is
the operating frequency of the processor external bus and requires TTL levels. All
external timing parameters except TDI, TDO, TMS, TRST# and PICD0
–
1 are
specified with respect to the rising edge of CLK.
This pin is 2.5 V-tolerant-only on the low-power embedded Pentium processor with
MMX technology.
It is recommended that CLK begin 150 ms after V
reaches its proper operating
level. This recommendation is only to assure the long term reliability of the device.
Table 6. Quick Pin Reference (Sheet 2 of 6)
Symbol
Type
Name and Function
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