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參數(shù)資料
| 型號： | Embedded Pentium 266 |
| 廠商： | Intel Corp. |
| 英文描述： | Low-Power Embedded Pentium Processor with MMX Technology(低能量嵌入式帶MMX技術(shù)奔騰處理器) |
| 中文描述： | 低功耗嵌入式處理器奔騰MMX技術(shù)（低能量嵌入式帶MMX公司的技術(shù)奔騰處理器） |
| 文件頁數(shù)： | 23/62頁 |
| 文件大?。?/td> | 1130K |
| 代理商： | EMBEDDED PENTIUM 266 |
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Low-Power Embedded Pentium
Processor with MMX Technology
Advance Information Datasheet
23
3.4
Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active
low inputs should be connected to V
CC3
. Unused active high inputs should be connected to GND
(V
SS
).
No Connect (NC) pins must remain unconnected. Connection of NC pins may result in component
failure or incompatibility with processor steppings.
3.5
Pin Quick Reference
This section gives a brief functional description of each pin. For a detailed description, see the
Hardware Interface chapter in the
Embedded Pentium
Processor Family Developer’s Manual.
Note:
All input pins must meet their AC/DC specifications to guarantee proper functional behavior.
The # symbol at the end of a signal name indicates that the active or asserted state occurs when the
signal is at a low voltage. When a # symbol is not present after the signal name, the signal is active,
or asserted at the high voltage level. Square brackets around a signal name indicate that the signal
is defined only at RESET.
The pins are classified as Input or Output based on their function in Master Mode. See the Error
Detection chapter of the
Embedded Pentium
Processor Family Developer’s Manual
(order
number 273204) for further information.
Table 6. Quick Pin Reference (Sheet 1 of 6)
Symbol
Type
Name and Function
A20M#
I
When the
address bit 20 mask
pin is asserted, the Pentium
processor with
MMX technology emulates the address wraparound at 1 Mbyte, which occurs on
the 8086. When A20M# is asserted, the processor masks physical address bit 20
(A20) before performing a lookup to the internal caches or driving a memory cycle
on the bus. The effect of A20M# is undefined in protected mode. A20M# must be
asserted only when the processor is in real mode.
A31–A3
I/O
As outputs, the
address
lines of the processor along with the byte enables define
the physical area of memory or I/O accessed. The external system drives the
inquire address to the processor on A31
–
A5.
ADS#
O
The
address status
indicates that a new valid bus cycle is currently being driven by
the processor.
AHOLD
I
In response to the assertion of
address hold
, the processor will stop driving the
address lines (A31
–
A3) and AP in the next clock. The rest of the bus will remain
active so data can be returned or driven for previously issued bus cycles.
AP
I/O
Address parity
is driven by the processor with even parity information on all
processor generated cycles in the same clock that the address is driven. Even
parity must be driven back to the processor during inquire cycles on this pin in the
same clock as EADS# to ensure that correct parity check status is indicated.
APCHK#
O
The
address parity check
status pin is asserted two clocks after EADS# is
sampled active if the processor has detected a parity error on the address bus
during inquire cycles. APCHK# will remain active for one clock each time a parity
error is detected.
BE7#
–
BE5#
BE4#
–
BE0#
O
I/O
The
byte enable
pins are used to determine which bytes must be written to external
memory, or which bytes were requested by the CPU for the current cycle. The byte
enables are driven in the same clock as the address lines (A31-3).
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