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參數(shù)資料
| 型號： | Embedded Pentium 266 |
| 廠商： | Intel Corp. |
| 英文描述： | Low-Power Embedded Pentium Processor with MMX Technology(低能量嵌入式帶MMX技術(shù)奔騰處理器) |
| 中文描述： | 低功耗嵌入式處理器奔騰MMX技術(shù)（低能量嵌入式帶MMX公司的技術(shù)奔騰處理器） |
| 文件頁數(shù)： | 30/62頁 |
| 文件大?。?/td> | 1130K |
| 代理商： | EMBEDDED PENTIUM 266 |
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Low-Power Embedded Pentium
Processor with MMX Technology
30
Advance Information Datasheet
The type field for low-power embedded Pentium processor with MMX technology is the same as
Pentium processor with MMX technology (type = 00H). The family field is the same as all other
Pentium processors (family = 5H). However, the model field is different: the Pentium processor
model number is 2H, the Pentium processor with MMX technology model number is 4H, and the
low-power embedded Pentium processor with MMX technology model number is 8H. The
stepping field indicates the revision number of a model. The stepping ID of A-step for the low-
power embedded Pentium processor with MMX technology is 1H. Stepping ID will be
documented in the low-power embedded Pentium processor with MMX technology stepping
information.
After masking the reserve bits, all low-power embedded Pentium processor with MMX
technology-based products will get a value of 0x008003BF (assuming the APIC is enabled at
boot), or 0x008001BF (when the APIC is disabled, using the APICEN boot pin) in EDX upon
completion of the CPUID instruction.
Table 8. EDX Bit Assignment Definitions for CPUID
Bit
Value
Comments
0
1
FPU: Floating-point Unit on-chip
1
1
VME: Virtual-8086 Mode Enhancements
2
1
DE: Debugging Extensions
3
1
PSE: Page Size Extension
4
1
TSC: Time Stamp Counter
5
1
MSR Pentium
Processor MSR
6
0
PAE: Physical Address Extension
7
1
MCE: Machine Check Exception
8
1
CX8: CMPXCHG8B Instruction
9
1
APIC: APIC on-chip
10–11
R
Reserved – Do not write to these bits or rely on their values
12
0
MTRR: Memory Type Range Registers
13
0
PGE: Page Global Enable
14
0
MCA: Machine Check Architecture
15–22
R
Reserved – Do not write to these bits or rely on their values
23
1
Intel Architecture with MMX technology supported
24–31
R
Reserved – Do not write to these bits or rely on their values
Indicates that APIC is present and hardware enabled (software disabling does not affect this bit).
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