參數(shù)資料
型號(hào)： EP9315-IBZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 46/106頁(yè)
文件大小： 0K
描述： IC ARM9 SOC ENH UNIV 352PBGA
標(biāo)準(zhǔn)包裝： 40
系列： EP9
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 200MHz
連通性： EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，PCMCIA，SPI，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 352-BGA
包裝： 托盤
配用： 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱： 598-1263
2-6
DS785UM1
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
2.2.3.3.2
Data Cache Enable
A write to bit 2 of CP15 register 1 will enable or disable the Data Cache (D-Cache)/Write
Buffer
The D-Cache may only be enabled when the MMU is enabled. All data accesses are
subject to MMU and permission checks
If disabled, current contents are ignored. If re-enabled before a reset, contents will be
unchanged, but may not be coherent with external memory. Depending on system
software, a clean and invalidate action may be required before re-enabling.
2.2.3.3.3
Write Buffer Enable
The Write Buffer is enabled via the page table entries in the MMU. The Write buffer
cannot be enabled unless the MMU is enabled.
2.2.4 Co-processor Interface
The MaverickCrunch co-processor is explained in detail in Chapter 3 on page 3-1. The
relationship between the ARM co-processor instructions and MaverickCrunch co-processor
is also explained in Chapter 3.
The ARM co-processor instruction set includes:
LDC - Load co-processor from memory
STC - Store co-processor register from memory
MRC - Move to ARM register from co-processor register
MCR - Move to co-processor register from ARM register
The ARM co-processor has sixteen (C0 through C15) 64-bit registers for data transfer and
data manipulation. See Chapter 3, Section 3.2 on page 3-8 for a code example.
2.2.5 AMBA AHB Bus Interface Overview
The AHB (Advanced High-Performance Bus) is the high-performance system backbone bus.
Figure 2-2 on page 2-7 shows a typical AMBA AHB System.
The AHB connects devices that require high bandwidth, such as DMA controllers, external
memory, and co-processors. The AHB supports:
Burst Transactions
Split Transactions
Bus Master hand-over to devices such as the MaverickCrunch co-processor or DMA
controller
Single clock edge operations
The APB (Advanced Peripheral Bus) is a lower bandwidth, but lower power, bus that
provides:
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