參數(shù)資料
型號(hào)： EP9315-IBZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 54/106頁(yè)
文件大?。?/td> 0K
描述： IC ARM9 SOC ENH UNIV 352PBGA
標(biāo)準(zhǔn)包裝： 40
系列： EP9
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 200MHz
連通性： EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤(pán)/觸摸屏，PCMCIA，SPI，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 352-BGA
包裝： 托盤(pán)
配用： 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱： 598-1263
DS785UM1
2-13
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
Note: Due to decoding optimization, the APB peripheral registers are aliased throughout each
peripherals register bank. Do not attemp to access an unspecified register within the bank.
2.3.3 APB Slave
An APB Slave responds to accesses initiated by bus masters. The slave uses signals from
the decoder to determine when it should respond to a bus access. All other signals required
for the access, such as the address and control information, are generated by the AHB-to-
APB Bridge.
2.3.4 Register Definitions
The ARM920T Core has thirty seven 32-bit internal registers, where some are modal and
some are banked. If operating in Thumb instructions state, the ARM Core must switch to
ARM instructions state before taking an exception. The return instruction will restore the ARM
Core to the Thumb state. Most tasks are executed out of User mode. The ARM920T Core’s
operating modes are shown in Table 2-4.
Table 2-5 illustrates the use of all registers for the ARM920T Core’s operating modes. Each
will bank or store a specific number of registers. Banked register information is not shared
between modes. FIQs bank the largest number of registers, and increase performance by
reducing the need to push/pop registers from the stack.
Table 2-4. ARM920T Core Operating Modes
Mode
Description
User
Unprivileged normal operating mode
FIQ
Fast interrupt (high priority) mode when FIQ is
asserted
IRQ
Interrupt request (normal) mode when IRQ is
asserted
Supervisor
Software interrupt instruction (SWI) or reset will
cause entry into this mode.
Abort:
Memory access violation will cause entry into this
mode.
Undef
Undefined instructions mode
System
Privileged mode. Uses same registers as User
mode
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