參數(shù)資料
型號： EP9315-IBZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 95/106頁
文件大?。?/td> 0K
描述： IC ARM9 SOC ENH UNIV 352PBGA
標(biāo)準(zhǔn)包裝： 40
系列： EP9
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 200MHz
連通性： EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，PCMCIA，SPI，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 352-BGA
包裝： 托盤
配用： 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱： 598-1263
DS785UM1
3-19
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
Moves from
accumulator
CDP
cfmv32al CRd, CRn
Move accumulator CRn[31:0] to 32-bit integer CRd[31:0]
cfmv32am CRd, CRn
Move accumulator CRn[63:32] to 32-bit integer CRd[31:0]
cfmv32ah CRd, CRn
Move accumulator CRn[71:64] to lower 8 bits of 32-bit integer CRd[31:0]
cfmv32a CRd, CRn
Saturate to 32-bit integer and move accumulator CRn[31:0] to 32-bit
integer CRd[31:0]
cfmv64a CRd, CRn
Saturate to 64-bit integer and move accumulator CRn[63:0] to 64-bit
integer CRd
Move to
DSPSC
CDP
cfmvsc32 CRd, CRn
Move CRd to DSPSC; CRn is ignored
Move from
DSPSC
cfmv32sc CRd, CRn
Moves DSPSC to CRd; CRn is ignored
Conversions
and copies
CDP
cfcpys CRd, CRn
Copy a single from CRn to CRd
cfcpyd CRd, CRn
Copy a double from CRn to CRd
cfcvtsd CRd, CRn
Convert a single in CRn to a double in CRd
cfcvtds CRd, CRn
Convert a double in CRn to a single in CRd
cfcvt32s CRd, CRn
Convert a 32-bit integer in CRn to a single in CRd
cfcvt32d CRd, CRn
Convert a 32-bit integer in CRn to a double in CRd
cfcvt64s CRd, CRn
Convert a 64-bit integer in CRn to a single in CRd
cfcvt64d CRd, CRn
Convert a 64-bit integer in CRn to a double in CRd
cfcvts32 CRd, CRn
Convert a single in CRn to a 32-bit integer in CRd
cfcvtd32 CRd, CRn
Convert a double in CRn to a 32-bit integer in CRd
cftruncs32 CRd, CRn
Truncate a single in CRn to a 32-bit integer in CRd
cftruncd32 CRd, CRn
Truncate a double in CRn to a 32-bit integer in CRd
Shifts
MCR
cfrshl32 CRm, CRn,
Rd
Shift 32-bit integer in CRn by two’s complement value in Rd and store in
CRm
cfrshl64 CRm, CRn,
Rd
Shift 64-bit integer in CRn by two’s complement value in Rd and store in
CRm
CDP
cfsh32 CRd, CRn,
<imm>
Shift 32-bit integer in CRn by <imm> bits and store in CRd, where <imm>
is between -32 and 31, inclusive
cfsh64 CRd, CRn,
<imm>
Shift 64-bit integer in CRn by <imm> bits and store in CRd, where <imm>
is between -32 and 31, inclusive
Table 3-10. MaverickCrunch Instruction Set (Continued)
Maverick
Crunch
Co-
Processor
Instruction
Type
ARM
Co-
Processor
Instruction
Type
Instruction
Description
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