參數(shù)資料
型號： EP9315-IBZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 87/106頁
文件大小： 0K
描述： IC ARM9 SOC ENH UNIV 352PBGA
標(biāo)準(zhǔn)包裝： 40
系列： EP9
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 200MHz
連通性： EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，PCMCIA，SPI，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 352-BGA
包裝： 托盤
配用： 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱： 598-1263
DS785UM1
3-11
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
DAID:
MaverickCrunch Architecture ID. This read-only value is
incre m e n ted for ea ch re vision of the ove r a l l
MaverickCrunch co-processor architecture. These bits are
“000” for this revision.
HVID:
Hardware Version ID. This read-only value is incremented
each time the hardware implementation of the architecture
named by DAID[2:0] is changed, typically done in
response to bugs. These bits are “000” for this version.
ISAT:
Integer Saturate Enable. This bit controls whether non-
ac cumul a t o r i nteger oper at i o ns , bo t h s i gned an d
unsigned, will saturate on overflow or underflow:
0 = Saturation enabled
1 = Saturation disabled
UI:
Unsigned Integer Enable. This bit controls whether non-
accumulator integer operations treat their operands as
signed or unsigned. It also determines the saturation value
if the ISAT bit is clear:
0 = Signed integers
1 = Unsigned integers
INT:
MaverickCrunch Interrupt. This bit indicates whether an
interrupt has occurred. This bit is identical to the external
interrupt signal:
0 = No interrupt signaled
1 = Interrupt signaled
AEXC:
Asynchronous Exception Enable. This bit determines
whether exceptions generated by the co-processor are
sign aled syn chron ou s ly or asyn chro nou sly to the
ARM920T. Synchronous exceptions force all data path
instructions to be serialized and to stall the ARM920T. If
exceptions are asynchronous, they are signalled by
assertion of the DSPINT output of the co-processor, which
may interrupt the ARM920T via the interrupt controller.
Enabling asynchronous exceptions does provide a
performance improvement, but makes it difficult for an
interrupt handler to determine the co-processor instruction
that caused the exception because the address of the
ins tru ctio n is n o t p r es erv e d . E x ce ptio ns m a y b e
individually enabled by other bits in this register (IXE, UFE,
OFE, and IOE). This bit has no effect if no exceptions are
enabled:
0 = Exceptions are synchronous
1 = Exceptions are asynchronous
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