參數(shù)資料
型號: EP9315-IBZ
廠商: Cirrus Logic Inc
文件頁數(shù): 8/106頁
文件大?。?/td> 0K
描述: IC ARM9 SOC ENH UNIV 352PBGA
標準包裝: 40
系列: EP9
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 200MHz
連通性: EBI/EMI,EIDE,以太網,I²C,IrDA,鍵盤/觸摸屏,PCMCIA,SPI,UART/USART,USB
外圍設備: AC'97,DMA,I²S,LCD,LED,MaverickKey,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據轉換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 352-BGA
包裝: 托盤
配用: 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱: 598-1263
DS785UM1
3-35
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
Bit Definitions:
CRd:
Destination register
CRn:
Source register
3.5.5 Shift Instructions
Shift 32-bit Integer
Description:
Shifts a 32-bit integer left or right. The shift count is a two’s complement
integer stored in an ARM register; the count is positive for left shifts and
negative for right shifts. This instruction may also be used to copy a 32-bit
integer from one register to another by using a shift value of 0.
Mnemonic:
CFRSHL32<cond> CRm, CRn, Rd
Bit Definitions:
CRm:
Destination register
CRn:
Source register
Rd:
Shift count register in ARM
Shift 64-bit Integer
Definition:
Shifts a 64-bit integer left or right. The shift count is a two’s complement
integer stored in an ARM register; the count is positive for left shifts and
negative for right shifts. This instruction may also be used to copy a 64-bit
integer from one register to another using a shift value of 0.
Mnemonic:
CFRSHL64<cond> CRm, CRn, Rd
Bit Definitions:
CRm:
Destination register
CRn:
Source register
Rd:
Shift count register in ARM
31:28
27:24
23:22
21
20
19:16
15:12
11:8
7:5
4
3:0
cond
1 1 1 0
0 0
0
CRn
Rd
0 1 0 1
0 1 0
1
CRm
31:28
27:24
23:22
21
20
19:16
15:12
11:8
7:5
4
3:0
cond
1 1 1 0
0 0
0
CRn
Rd
0 1 0 1
0 1 1
1
CRm
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