- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16522 > EVAL-ADAU1381Z (Analog Devices Inc)BOARD EVALUATION FOR ADAU1381 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADAU1381Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADAU1381 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADAU1381 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADAU1381BCBZ-RL7DKR-ND - IC AUDIO CODEC STEREO LN 30WLCSP ADAU1381BCBZ-RL7CT-ND - IC AUDIO CODEC STEREO LN 30WLCSP ADAU1381BCBZ-RL-ND - IC AUDIO CODEC STEREO LN 30WLCSP ADAU1381BCPZ-RL7-ND - IC AUDIO CODEC STEREO LN 32LFCSP ADAU1381BCPZ-RL-ND - IC AUDIO CODEC STEREO LN 32LFCSP ADAU1381BCBZ-RL7TR-ND - IC AUDIO CODEC STEREO LN 30WLCSP ADAU1381BCPZ-ND - IC AUDIO CODEC STEREO LN 32LFCSP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
ADAU1381
Rev. B | Page 45 of 84
Register 16385 (0x4001), Regulator Control
Bits[2:1], Regulator Output Level
These bits set the regulated voltage output for the digital core,
DVDDOUT. After the initialization sequence has completed,
the regulator output is set to 1.4 V. The recommended regulator
output level when the device begins to process audio is 1.5 V.
Therefore, this register should be set to 1.5 V when the sound
engine is being configured.
Register 16386 (0x4002), PLL Control
This is a 48-bit register that must be written to in a single burst
write. PLL operating parameters are used to scale the MCLK
input to the desired clock core in order to obtain an appropriate
PLL clock (PLL output frequency). The PLL can be configured
for either fractional or integer-N type MCLK inputs.
Bits[47:40], Denominator MSB
Byte 1, M[15:8] of the denominator (M) for fractional part of feed-
back divider. This is concatenated with Denominator LSB, M[7:0].
Bits[39:32], Denominator LSB
Byte 0, M[7:0] of the denominator (M) for fractional part of feed-
back divider. This is concatenated with Denominator MSB, M[15:8].
Bits[31:24], Numerator MSB
Byte 1, N[15:8] of the numerator (N) for fractional part of the feed-
back divider. This is concatenated with Numerator LSB, N[7:0].
Bits[23:16], Numerator LSB
Byte 0, N[7:0] of the numerator (N) for fractional part of the feed-
back divider. This is concatenated with Numerator MSB, N[15:8].
Bits[14:11], Integer
Integer (R) parameter used in both integer-N and fractional
PLL operation. This value must be between 2 and 8.
Bits[10:9], Input Divider
The input divider (X) divides the input clock to offer a wider
range of input clocks.
Bit 8, PLL Type
This selects the type of PLL operation, fractional or integer-N.
Fractional Type PLL
Fractional type MCLK inputs are scaled to the corresponding
desired core clock input using the parameters outlined in Table 33
and Table 34 as examples of typical base sampling frequencies
(44.1 kHz and 48 kHz). A numerical-controlled oscillator is
used to divide the PLL_CLK by a mixed number given by the
addition of the integer part (R) and fractional part (N/M).
For example, if the MCLK is 12 MHz, the required clock is
12.288 MHz, and fS is 48 kHz, then the PLL clock is 49.152 MHz
because PLL clock is always 1024 × fS; therefore,
PLL Clock/MCLK = 4.096 = 4 + (12/125) = R + (N/M)
In this case, the input divider is X = 1.
This allows the MCLK input to emulate the desired required clock
and output a 49.152 MHz PLL clock. Figure 30 shows how the PLL
uses the parameters to emulate the required 12.288 MHz clock.
Integer-N Type PLL
Integer-N type MCLK inputs are any integer multiple of the
desired core clock. The fractional part (N/M) is 0; however, the
PLL type bit must be set for integer-N.
Bit 1, PLL Lock
The PLL lock bit is a read-only bit. Reading a 1 from this bit
indicates that the PLL has locked to the input master clock.
Bit 0, PLL Enable
This bit enables the PLL.
Table 31. Regulator Control Register
Bits
Description
Default
[7:3]
Reserved
[2:1]
Regulator output level
01
00: 1.5 V
01: 1.4 V
10: 1.6 V
11: 1.7 V
0
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16V2751IM-0B-EB | EVAL BOARD FOR V2751 48TQFP |
| LBR2518T100M | INDUCTOR WOUND 10UH 235MA 1007 |
| VE-JVX-EZ-S | CONVERTER MOD DC/DC 5.2V 25W |
| A3CCH-2418G | IDC CABLE - AKC24H/AE24G/AKC24H |
| BA6238A | IC DRIVER REV MOTOR 2CH HSIP10 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1401AEBZ | 功能描述:BOARD EVAL FOR ADAU1401A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADAU1401EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| EVAL-ADAU1401EBZ | 功能描述:BOARD EVAL FOR ADAU1401 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADAU1401-EBZ | 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| EVAL-ADAU1442EBZ | 功能描述:BOARD EVAL FOR ADAU1442 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。