參數(shù)資料
型號(hào)： EVAL-ADAU1381Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 49/84頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADAU1381
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻編解碼器
嵌入式： 否
已用 IC / 零件： ADAU1381
已供物品： 板
相關(guān)產(chǎn)品： ADAU1381BCBZ-RL7DKR-ND - IC AUDIO CODEC STEREO LN 30WLCSP
ADAU1381BCBZ-RL7CT-ND - IC AUDIO CODEC STEREO LN 30WLCSP
ADAU1381BCBZ-RL-ND - IC AUDIO CODEC STEREO LN 30WLCSP
ADAU1381BCPZ-RL7-ND - IC AUDIO CODEC STEREO LN 32LFCSP
ADAU1381BCPZ-RL-ND - IC AUDIO CODEC STEREO LN 32LFCSP
ADAU1381BCBZ-RL7TR-ND - IC AUDIO CODEC STEREO LN 30WLCSP
ADAU1381BCPZ-ND - IC AUDIO CODEC STEREO LN 32LFCSP
ADAU1381
Rev. B | Page 53 of 84
SERIAL PORT CONFIGURATION
Register 16405 (0x4015), Serial Port Control 0
Bit 5, LRCLK Mode
This bit sets the serial port frame clock (LRCLK) as either a
50% duty cycle waveform or a pulse synchronization waveform.
When in slave mode, the pulse should be at least 1 BCLK cycle
wide to guarantee proper data transfer.
Bit 4, BCLK Polarity
This bit sets the polarity of the bit clock (BCLK) signal. This
setting determines whether the data and frame clock signals
change on a rising (+) or falling () edge of the BCLK signal
(see Figure 57). Standard I2S signals use negative BCLK polarity.
Bit 3, LRCLK Polarity
The polarity of LRCLK determines whether the left stereo channel
is initiated on a rising (+) or falling () edge of the LRCLK signal
(see Figure 58). Standard I2S signals use negative LRCLK polarity.
Bits[2:1], Channels per Frame
These bits set the number of channels contained in the data stream
(see Figure 59). The possible choices are stereo (used in standard
I2S signals), TDM 4 (a 4-channel time division multiplexed stream),
or TDM 8 (an 8-channel time division multiplexed stream). The
TDM output modes are simply multichannel data streams, and
the data pin does not become high impedance during periods
when it is not outputting data.
Within a TDM stream, channels are grouped by pair, as shown
Bit 0, Serial Data Port Mode
This bit sets the clock pins as either master or slave. Both
LRCLK and BCLK are the bus master of the serial port when
master mode is enabled.
Table 40. Serial Port Control 0 Register
Bits
Description
Default
[7:6]
Reserved
5
LRCLK mode
0
0: 50% duty cycle clock
1: pulse mode; pulse should be at least 1 BCLK wide
4
BCLK polarity
0
0: data changes on falling () edge
1: data changes on rising (+) edge
3
LRCLK polarity
0
0: left frame starts on falling () edge
1: left frame starts on rising (+) edge
[2:1]
Channels per frame
00
00: stereo (two channels)
01: TDM 4 (four channels)
10: TDM 8 (eight channels)
11: reserved
0
Serial data port mode
0
0: slave
1: master
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