參數(shù)資料
型號： EVAL-ADAU1381Z
廠商： Analog Devices Inc
文件頁數(shù)： 58/84頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADAU1381
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻編解碼器
嵌入式： 否
已用 IC / 零件： ADAU1381
已供物品： 板
相關(guān)產(chǎn)品： ADAU1381BCBZ-RL7DKR-ND - IC AUDIO CODEC STEREO LN 30WLCSP
ADAU1381BCBZ-RL7CT-ND - IC AUDIO CODEC STEREO LN 30WLCSP
ADAU1381BCBZ-RL-ND - IC AUDIO CODEC STEREO LN 30WLCSP
ADAU1381BCPZ-RL7-ND - IC AUDIO CODEC STEREO LN 32LFCSP
ADAU1381BCPZ-RL-ND - IC AUDIO CODEC STEREO LN 32LFCSP
ADAU1381BCBZ-RL7TR-ND - IC AUDIO CODEC STEREO LN 30WLCSP
ADAU1381BCPZ-ND - IC AUDIO CODEC STEREO LN 32LFCSP
ADAU1381
Rev. B | Page 61 of 84
Register 16409 (0x4019), ADC Control
Bit 6, Invert Input Polarity
This bit enables an optional polarity inverter in the ADC path,
which is an amplifier with a gain of 1, representing a 180°
phase shift.
Bit 5, High-Pass Filter Select
This bit enables an optional high-pass filter in the ADC path,
with a cutoff frequency of 2 Hz when fS = 48 kHz. The cutoff
frequency scales linearly with fS.
Bit 4, Digital Microphone Data Polarity Swap
This bit inverts the polarity of valid data states for the digital
microphone data stream. A typical PDM microphone can drive
its data output pin either high or low, not both. This bit must be
configured accordingly to recognize a valid output state of the
microphone. The default is negative, meaning that a digital
logic low signal is recognized by the ADAU1381 as a pulse in
the PDM signal.
Bit 3, Digital Microphone Channel Swap
This bit allows the left and right channels of the digital microphone
input to swap. Standard mode is the left channel on the rising
edge and the right channel on the falling edge. Swapped mode is
the right channel on the rising edge and the left channel on the
falling edge.
Bit 2, Digital Microphone Input Select
This bit must be enabled in order to use the digital microphone
inputs. When this bit is asserted, the on-chip ADCs are off, BCLK
is the master at 128 × fS, and ADC_SDATA is expected to have
the left and right channels interleaved. This bit must be disabled
to use the ADCs.
Bits[1:0], ADC Enable
These bits must be configured to use the ADCs. ADC channels
can be enabled or disabled individually.
Table 44. ADC Control Register
Bits
Description
Default
7
Reserved
6
Invert input polarity
0
0: normal
1: inverted
5
High-pass filter select
0
0: disabled
1: enabled
4
Digital microphone data polarity swap
0
0: negative
1: positive
3
Digital microphone channel swap
0
0: standard mode
1: swapped mode
2
Digital microphone input select
0
0: digital microphone input off
1: select digital microphone input, ADCs off
[1:0]
ADC enable
00
00: both off
01: left on
10: right on
11: both on
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