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參數(shù)資料
| 型號： | FMS7401 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 數(shù)字電源控制器 |
| 文件頁數(shù)： | 10/80頁 |
| 文件大小： | 1535K |
| 代理商： | FMS7401 |
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FMS7401/7401L
PRODUCT SPECIFICATION
10
REV. 1.0.2 6/23/04
2
Clock Circuit
The FMS7401/7401L may be clocked using its internal oscillator circuit or using an external digital clock signal. The desired
clock source is selectable by the CMODE bit of the Initialization Register 1.
updated and the desired clock source (also called the device reference clock or F
are defaulted from the factory to use the internal oscillator as their main system instruction clock source. After power-up, the
internal oscillator runs continuously unless entering Halt Mode or using an external clock source.
1
During the reset sequence, the CMODE bit is
) takes control of the device. All devices
RCLK1
Table 2. CMODE Bit Definition
The internal oscillator signal is factory trimmed to yield the F
of the datasheet. If the external digital clock is selected, the input signal must have a 50/50 duty cycle, can range from DC to
the F
OSC
, and must be available upon power-up. When the device is driven using an external clock source, the clock input to the
device should be provided through the AIN3/G1 input.
OSC
frequency as specified in the
Electrical Characteristics
section
Once the source of F
the Programmable Comparator circuit, and is divided-by-2 to be used as the main system instruction clock (F
(see
Figure 3
and
Figure 4
).
RCLK1
is selected, the clock is then used as the reference clock for the PLL, the clock to the digital filter in
ICLK
) of the device
2.1
The FMS7401/7401L has an internal digital clock multiplier (PLL) that steps-up the F
tor of 32. The multiplied PLL output is then divided by a factor of 1, 2, 4, and 8 in order to generate its programmable output
frequencies that may be used as the main system instruction clock or by the PWM Timer 1 circuit. The PLL provides the ability
to run the PWM Timer 1 circuit at a frequency as high as 64MHz while the rest of the device operates at a much slower fre-
quency keeping the total current consumption low.
PLL
RCLK1
frequency by a multiplication fac-
The reference clock of the PLL is defined by the F
signal. In order to yield the proper output frequencies offered by the PLL, F
fied in the
Electrical Characteristics
section of the datasheet. In the case that F
the REFBY2 bit in the ADCNTRL2 register
quency of the F
RCLK2
signal. Once the REFBY2 bit is set, the F
grammable Comparator circuit operates at a F
must be supplied at the specified F
OSC
frequency in order to meet the specified F
RCLK2
signal (as shown in
Figure 3
and
Figure 4
) and sourced by the F
must operate at the F
is operating at the upper F
must be set in order to divide the F
RCLK1
signal that drives the PLL and digital filter in the Pro-
/2 frequency. If an external digital clock is sourcing F
frequency of the F
RCLK1
RCLK2
PLL
frequency as speci-
frequency,
RCLK1
OSC
2
3
by 2 to yield the appropriate F
PLL
fre-
RCLK2
RCLK1
RCLK1
, the input signal
signal.
PLL
RCLK2
Table 3. PLL Frequency Selection (F
PLL
/F
OSC
= 2MHz)
The PLL outputs may be used to clock both the PWM Timer 1 circuit and the main system clock. However, the PLL must first
be enabled by setting the PLLEN bit of the PSCALE register.
Once set, the PLL is turned on and begins the locking phase.
Before using any of the PLL outputs, software must wait the T
PLL_LOCK
quency and in phase. The PLLEN bit may not be changed while the PWM Timer 1 circuit is in run mode.
to this bit during this condition will not change its value.
4
to ensure that the PLL is locked into its appropriate fre-
5
Any write attempts
The PWM Timer 1 circuit may be clocked either by the PLL’s F
bit of the PSCALE register
selects between the PLL’s F
not be set if the PLL is not enabled (PLLEN=0) or changed while the PWM Timer 1 circuit is in run mode.
5
Any write attempts
to this bit during these conditions will not change its value.
PWMCLK
output or by the main system clock (F
PWMCLK
output (if FSEL=1) or F
ICLK
(if FSEL=0). The FSEL bit may
ICLK
). The FSEL
4
CMODE
F
RCLK1
Clock Source
0
Internal Oscillator (@ F
OSC
)
1
External digital clock (G1/AIN3)
FS[1:0]
F
RCLK2
F
ICLK
(FMODE = 0)
F
ICLK
(FMODE = 1)
F
PWMCLK
0
0
2 MHz
1 MHz
8 MHz
8 MHz
0
1
2 MHz
1 MHz
8 MHz
16 MHz
1
0
2 MHz
1 MHz
8 MHz
32 MHz
1
1
2 MHz
1 MHz
8 MHz
64 MHz
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