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參數(shù)資料
| 型號： | FMS7401 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 數(shù)字電源控制器 |
| 文件頁數(shù)： | 11/80頁 |
| 文件大?。?/td> | 1535K |
| 代理商： | FMS7401 |
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PRODUCT SPECIFICATION
FMS7401/7401L
REV. 1.0.2 6/23/04
11
The FS[1:0] bits of the PSCALE register
4
select the divide factor for the F
PWMCLK
output (see
Table 3
). The FS bits may be
changed by software at any time; however, if the PWM Timer 1 circuit is in run mode the FS[1:0] value will not change the
F
PWMCLK
output frequency until after the PWM cycle ends (once the TMR1 counter overflows). The last FS[1:0] value at the
PWM cycle end time will dictate the divide factor of the F
PWMCLK
output for the next PWM cycle. When reading the FS[1:0],
the value reported will be the last value written by software (it may not necessarily reflect the divide factor for the current
PWM cycle).
The main system instruction clock (F
ICLK
) source may be provided by the internal oscillator (F
OSC
) or the PLL’s F
(FS=0)
output
with the same divide factor as the FS[1:0] = 00 selection.
6
The FMODE bit of the PSCALE register
4
selects between the F
(FS=0)
(if FMODE=1) or F
RCLK1
divided-by-2 signal. With the FMODE bit enabled, it is possible to execute instructions at a speed
eight times faster than the standard. The FMODE bit may not be set if the PLL is not enabled.
5
Any attempts to write to
FMODE while PLLEN=0 will force FMODE=0 ignoring any set instruction. Once the PLL has been enabled, software may
change F
ICLK
’s source on-the-fly during normal instruction execution in order to speed-up a particular action.
In order to synchronously disable the PLL clocking structure, software must clear FSEL and FMODE before clearing the
PLLEN bit in order to disable the PLL successfully e.g. using separate instructions like “RBIT PLLEN, PSCALE.” There are
also special conditions for Halt/Idle power saving modes that must also be considered. Please refer to the
Power Saving Modes
section of the datasheet for details.
Figure 3. Internal Clock Scheme
F
PWMCLK
Digital
C
lock
M
u
lti
p
li
er
(
PLL
)
F
S[1]
F
S[
0
]
Di
v
i
d
e
by
2
PLL
EN
F
S
E
L
F
M
O
D
E
R
E
F
BY
2
F
I
CLK
Y
S
e
l
A
B
A
B
Y
S
e
l
A
B
S
e
l
Y
F
R
CLK
1
F
(
F
S
=
0
)
F
R
CLK
2
C
lock
i
mm
i
n
g
I
N
I
T
2
I
n
t
er
n
al
O
s
cillato
r
F
T
1
CLK
(
F
PLL
)
(
F
O
S
C
)
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