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參數(shù)資料
| 型號(hào)： | FMS7401 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 數(shù)字電源控制器 |
| 文件頁數(shù)： | 37/80頁 |
| 文件大?。?/td> | 1535K |
| 代理商： | FMS7401 |
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PRODUCT SPECIFICATION
FMS7401/7401L
REV. 1.0.2 6/23/04
37
Table 16. Timer 1 Control (T1CNTRL) Register Bit Definitions
Table 17. Timer 1 Mode Configuration Bits
6.2
In PWM Mode, the Timer 1 circuit may be configured to generate pulses of a specified duty cycle and period on the T1HS1
(G0), T1HS2 (G5), and/or ADSTROBE (G1) timer outputs. The 12-bit TMR1 counter increments at the F
T1CLK
clock rate
defined by the FSEL bit of the PSCALE register. Refer to the previous
PSCALE Register and Timer 1 Clock Configuration
section
of the datasheet for details.
Pulse Width Modulation (PWM) Mode
A PWM cycle begins with the TMR1 counter incrementing from 0x000 until it matches the value stored in the T1RA register.
At this point, the TMR1 counter completes its T1RA count and overflows (a transitions from T1RA to 0x000) setting the
T1PND flag of the T1CNTRL register ending the PWM cycle. The Timer 1 circuit has two additional TMR1 compare
(T1CMPA and T1CMPB) registers used to generate the T1HS1, T1HS2, and ADSTROBE output signals. All three output
signals are initialized to a resting (off) state. Once the TMR1 counter is enabled (by setting the T1C0 bit of the T1CNTRL
register), both compare registers are matched against the incrementing TMR1 counter. When the TMR1 completes its count
equal to the value stored in the T1CMPA and T1CMPB registers, the T1HS1, T1HS2, and ADSTROBE output signals are set
to an active (on) state until the TMR1 counter matches the value stored in the T1RA compare register (overflows). Once the
TMR1 counter overflows, the output signals are cleared returning them to a resting (off) state. Refer to
Figure 11
for a Timer 1
PWM Mode block diagram.
T1CNTRL Register (addr. 0xAE)
Bit 4
T1C0
Bit 7
T1C3
Bit 6
T1C2
Bit 5
T1C1
Bit 3
T1PND
Bit 2
T1EN
Bit 1
X
Bit 0
T1BOUT
Bit
T1C3
T1C2
T1C1
T1C0
Description
Timer 1 Mode Configuration Bit. Refer to
Table 17
for details.
Timer 1 Mode Configuration Bit. Refer to
Table 17
for details.
Timer 1 Mode Configuration Bit. Refer to
Table 17
for details.
PWM Mode
(0) Stop the PWM Timer 1 circuit.
(1) Start the PWM Timer 1 circuit.
Input Capture Mode
(0) Timer 1’s TMR1 overflow pending flag is cleared.
(1) Timer 1’s TMR1 overflow pending flag is triggered.
PWM Mode
(0) Timer 1’s TMR1 overflow pending flag is cleared.
(1) Timer 1’s TMR1 overflow pending flag is triggered.
Input Capture Mode
(0) Timer 1 capture pending flag is cleared.
(1) Timer 1 capture pending flag is triggered.
(0) Disables Timer 1 hardware interrupts.
(1) Enables Timer 1 hardware interrupts.
(0) Retain normal I/O function of the G1/AIN3 pin.
(1) Enables Timer 1’s ADSTROBE output to be sent to the G1 output port.
T1PND
T1EN
T1BOUT
T1C3
0
0
0
0
1
T1C2
0
1
0
1
0
T1C1
0
1
1
0
0
Timer Mode Source
Interrupt
TMR1 Overflow
TMR1 Overflow
TMR1 Overflow
TMR1 Overflow
TMR1 Overflow
T1HS2 rising-edge
TMR1 Overflow
T1HS2 rising-edge
TMR1 Overflow
T1HS2 falling-edge
TMR1 Overflow
T1HS2 falling-edge
Timer count on
Prescaler Input
Prescaler Input
Prescaler Input
Prescaler Input
Prescaler Input
PWM mode no output toggle
PWM mode T1HS1 and T1HS2 toggle
PWM mode T1HS1 toggle
PWM mode T1HS2 toggle
Capture mode no T1HS1 toggle
1
0
1
Capture mode with T1HS1 toggle
Prescaler Input
1
1
0
Capture mode no T1HS1 toggle
Prescaler Input
1
1
1
Capture mode with T1HS1 toggle
Prescaler Input
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