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參數(shù)資料
| 型號： | FMS7401 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 數(shù)字電源控制器 |
| 文件頁數(shù)： | 31/80頁 |
| 文件大?。?/td> | 1535K |
| 代理商： | FMS7401 |
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PRODUCT SPECIFICATION
FMS7401/7401L
REV. 1.0.2 6/23/04
31
Table 11. Digital Delay (DDELAY) Register Bit Definitions
Figure 10. Digital Delay Timing
1. Refer to the
ADC Circuit
section of the datasheet for additional details.
2. Refer to the
I/O Ports
section of the datasheet for details.
3. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the
8-Bit
Microcontroller Core
section of the datasheet for details.
4. Refer to the
Clock Circuit
section of the datasheet for details regarding the F
RCLK2
clock.
DDELAY Register (addr. 0xA2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COMPEN
PWMINT
EPWM
OFFMODE
DD[3:0]
Bit
Description
COMPEN
(0) Disable the Programmable Comparator circuit.
(1) Enable the Programmable Comparator circuit.
PWMINT
(0) The input of the G6 MIW circuit network is the G6/-A
IN
device pin.
(1) The input of the G6 MIW circuit network is the PWMOFF output signal (not the G6/-A
IN
device pin).
EPWM
(0) Enables the Digital Delay Filter circuit. The PWMOFF output is triggered by C
OUT
after the programmed delay (T
DDELAY
).
(1) Disables the Digital Delay Filter circuit and the PWMOFF output signal.
OFFMODE
(0) PWM outputs switched off and Timer 1 stops after a comparator detection with delay.
(1) PWM outputs switched off for the current PWM cycle only.
DD[3:0]
Digital delay after C
OUT
triggers high, T
DDELAY
= DD (1/F
RCLK2
)
T
DDELAY
Start
Sample
Comparator
Output
Digital
Delay
PWMOFF
T1HS1
T1HS2
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