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FMS7401/7401L
PRODUCT SPECIFICATION
26
REV. 1.0.2 6/23/04
Bits 7-2 (CL[5:0]) is the comparator voltage threshold level selection bits of the Comparator Control (COMP) register. The CL
bits may be programmed to select one of the voltage threshold levels as the inverting input of the analog comparator. Refer to
Table 9
and
Table 10
for a detailed list of voltages.
Bit 1 of the Comparator Control (COMP) register is the Programmable Comparator circuit’s voltage loop (VLOOP) configura-
tion enable bit. If VLOOP=0, the Programmable Comparator circuit is configured to compare the analog G4/AIN0 or G2/AIN2
input (COMPSEL=0 or 1) to one of the 63 voltage threshold levels. If VLOOP=1, enables the voltage loop configuration where
the analog G4/AIN0 or G2/AIN2 input (COMPSEL=0 or 1) to the Uncommitted (Error) Amplifier output (A
OUT
).
Bit 7 of the Digital Delay (DDELAY) register is the Programmable Comparator circuit enable (COMPEN) bit. If COMPEN=0,
the Programmable Comparator circuit is disabled and the C
OUT
signal is low. If COMPEN=1, the Programmable Comparator
circuit is enabled and the C
OUT
signal generated by the comparison of the two inputs.
The comparator output (C
OUT
) signal is latched by the main system instruction (F
ICLK
) clock into bit 0 (COUT) of the Compar-
ator Control (COMP) register. Software may only read the COUT bit to monitor the comparator’s activity. The COUT bit
cannot cause a microcontroller hardware interrupt or perform any other action.
Figure 8. Programmable Comparator Block Diagram (VLOOP = 0)
DDELAY
Register
7
C
L
[5]
1
V
L
OOP
0
C
O
UT
A
d
ju
st
Re
f
ere
nc
e
V
ol
t
a
ge
C
o
mp
a
r
a
t
r
C
tr
ol
(
C
O
M
P
)
Register
G4/
A
IN
0
_
+
D
IGI
T
AL
DELAY
C
I
R
C
U
I
T
3
2
1
0
P
W
M
O
FF
(
WK
E
N
[
6
]
)
DD
[
3
]
DD
[
2
]
DD
[
1
]
DD
[
0
]
F
R
C
L
K
2
5
E
P
W
M
E
n
6
C
L
[
4
]
5
C
L
[
3
]
4
C
L
[
2
]
3
C
L
[
1
]
2
C
L
[
0
]
A
C
H
5
G
2
/
A
IN
2
C
O
M
P
S
EL
AD
C
N
T
R
L
2
[
6
]
C
o
mp
a
r
a
t
o
r
C
O
UT