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參數(shù)資料
| 型號： | FMS7401LVN14 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 20/80頁 |
| 文件大?。?/td> | 1535K |
| 代理商： | FMS7401LVN14 |
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FMS7401/7401L
PRODUCT SPECIFICATION
20
REV. 1.0.2 6/23/04
options must be prepared prior to setting the ENDAS bit. Refer to the following
ADC Gated Auto-sampling Mode
section for
additional details. The ADSTROBE signal is generated by the PWM Timer 1 circuit and is configured using its T1CMPB and
T1RA registers. Refer to the
PWM Timer 1 Circuit
section of the datasheet for details regarding its operation. If ENDAS=0,
the ADC circuit is configured to accept only ADC start commands issued by software when setting the ASTART bit of the
ADCNTRL1 register to 1. Refer to the following
ADC Conversion Modes
section for additional details.
Bits 3 and 2 (ASPEED[1:0]) of the ADCNTRL2 register selects the divide factor (1, 2, 4, or 8) to slow the F
ADCLK
clock
extending the ADC conversion cycle time. In most cases, the F
ADCLK
clock division is performed to improve the ADC
conversion accuracy. Refer to the following
ADC Conversion Clock Configuration
section for addition details.
Bit 1 of the ADCNTRL2 register is the Current Source Generator Enable (ENIS) bit. If ENIS=0, the Current Source Generator
circuit is disabled and its G3/AIN1 pin may be used as a normal I/O port or as a standard ADC conversion input through the
analog ACH2 channel. If ENIS=1, the Current Source Generator circuit is enabled and its pin connection must be configured as
a tri-state input bypassing the I/O circuitry.
9
If the ADC circuit is performing a conversion on the analog ACH2 input when
driven by the Current Source Generator, software must avoid clearing the ENIS bit. Refer to the following
Current Source
Generator
section for additional details.
Bit 0 (GAIN) of the ADCNTRL2 register is the autozero amplifier enable bit. If GAIN=0, the autozero amplifier with its gain
16 circuitry is disabled where its G4/AIN0 pin connections may be used as a normal I/O port. The G4/AIN0 pin may still be
used as a standard ADC conversion input through the analog ACH1 channel. If GAIN =1, the autozero amplifier with its gain
16 circuitry is enabled and its G4/AIN0 pin connection must be configured as a tri-state input where G4/AIN0 is the non-
inverting and SR_GND is the inverting input of the amplifier.
9
Software may write to the GAIN bit at any time; however, the
actual GAIN enable signal will not change while an ADC conversion is in progress. If a read command is issued while a con-
version is in progress, the current value of the GAIN bit may not necessarily reflect the actual state of the GAIN enable signal.
The last value of the GAIN bit written by software at the time of the ADC conversion trigger, dictates the state of the GAIN
enable signal for the triggered ADC conversion cycle. Refer to the following
Autozero Amplifier
section for additional details.
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