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參數(shù)資料
| 型號(hào)： | FMS7401LVN14 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 46/80頁(yè) |
| 文件大?。?/td> | 1535K |
| 代理商： | FMS7401LVN14 |
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FMS7401/7401L
PRODUCT SPECIFICATION
46
REV. 1.0.2 6/23/04
The MIW circuit can be used with the I/O ports configured as both an input and output. The MIW configuration and function is
the same for both I/O configurations. However, when using the MIW circuit to wake the device from Halt/Idle Mode the
wakeup I/O port must be configured as an input, otherwise the device will never exit the mode.
Table 22. Multi-input Wakeup (MIW) Register Bit Assignments
Figure 16. Multi-input Wakeup (MIW) Block Diagram
6
1. Refer to the
Power Saving Modes
section of the datasheet for detail regarding Halt and Idle Mode.
2. Refer to
Table 30
of the
Device Memory
section of the datasheet for the detailed memory map.
3. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the
8-Bit
Microcontroller Core
section of the datasheet for details.
4. No other hardware interrupts will be executed, aside from the software interrupt instruction, until the MIW hardware interrupt is no longer executed. Refer to the
8-Bit Microcontroller Core
section of the datasheet for details.
5. Available only on the 14-pin package option.
6. The PWMOFF and PWMINT signals are the outputs from the Programmable Comparator’s Digital Filter circuit. Refer to
Programmable Comparator Circuit
section
of the datasheet for details.
WKEN, WKEDG, WKPND Registers (addr. 0xB1, 0xAF, 0xB0)
Bit 7
G7
5
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWMOFF
6
/G6
5
G5
G4
G3
G2
G1
G0
EDGEI
WAKEOUT
Data Bus
7
0
WKEN[7:0]
7
0
WKEDG[7:0]
WKPND[7:0]
G0
WKINTEN
G7
G6
Y
A
B
Sel
PWMOFF
PWMINT
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