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參數(shù)資料
| 型號(hào)： | FMS7401LVN14 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 60/80頁(yè) |
| 文件大?。?/td> | 1535K |
| 代理商： | FMS7401LVN14 |
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FMS7401/7401L
PRODUCT SPECIFICATION
60
REV. 1.0.2 6/23/04
12 In-circuit Programming Specification
The FMS7401/7401L supports in-circuit programming of all internal memory mapped registers including the data EEPROM, code
EEPROM, and initialization registers. In-circuit programming consists of a 4-wire serial interface used to place the device in pro-
gramming mode and issue all programming commands.
1
The external programmer should follow the device pinout
1
defined in
Fig-
ure 19
and the timing rules defined by the parameters listed in
Table 31
as shown in
Figure 20
and
Figure 21
.
Figure 19. Programming Mode Pin Configurations
Table 32. Programming Interface Electrical Characteristics
2
12.1 Programming Mode Interface
In order to place the device in programming mode, a 10-bit opcode (0x34B) must be shifted into the device during its system
reset. A system reset may be triggered during the device power-up by the Power-on Reset circuit or with the device already
powered with a low pulse on the device RESET pin.
3
After power-up, the external programmer must shift in the 10-bit opcode
before the system reset sequence completes. If the correct opcode is shifted, the device will automatically enter programming
mode once the system reset sequence has completed.
The 10-bit opcode is serially shifted with the most significant bit (MSB) first into the device through the SHIFT_IN pin. Each
opcode data bit must be valid by T
DIS
before the rising edge of CLOCK. As the opcode is shifted, the current 10-bit pattern is
compared against 0x34B. If the 10-bit pattern is a match, the device will set the program mode flag and the device will enter
programming mode once the system reset sequence completes (see
Figure 20
).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
T
HI
CLOCK high time
25 °C
500
DC
nS
T
LO
CLOCK low time
25 °C
500
DC
nS
T
DIS
SHIFT_IN setup time
25 °C
100
nS
T
DIH
SHIFT_IN hold time
25 °C
100
nS
T
DOS
SHIFT_OUT setup time
25 °C
100
nS
T
DOH
SHIFT_OUT hold time
25 °C
900
nS
T
ACCESS
SHIFT_OUT sample time
25 °C
500
DC
nS
T
LOAD1
, T
LOAD2
,
T
LOAD3
, T
LOAD4
Loading time
25 °C
5
μS
T
READY
EEPROM write time
25 °C
3.7
mS
T
RESET
System Reset time
25 °C
3.7
mS
SHIFT_IN
LOAD
CLOCK
SHIFT_OUT
NC/VCC
GND
VCC
NC
1
2
6
5
7
8
3
4
NC/VCC
SHIFT_OUT
GND
SHIFT_IN
LOAD
VCC
NC
CLOCK
1
2
6
5
7
8
3
4
VCC
NC/VCC
VDD
SHIFT_IN
LOAD
NC
CLOCK
SHIFT_OUT
NC
GND
NC
NC
RESET
1
2
6
7
8
9
13
14
3
4
11
12
5
10
AGND
FMS7401L 8-Pin PDIP/SOIC
FMS7401L 8-Pin TSSOP
FMS7401L 14-Pin PDIP/SOIC/TSSOP
FMS7401 14-Pin PDIP/SOIC/TSSOP
SHIFT_IN
LOAD
NC
CLOCK
SHIFT_OUT
NC
GND
NC
VCC
NC/VCC
NC/VCC
NC
RESET
1
2
6
7
8
9
13
14
3
4
11
12
5
10
NC/GND
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