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參數(shù)資料
| 型號： | FUSB2805MLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 28/49頁 |
| 文件大小： | 0K |
| 描述： | TXRX USB2.0 HS OTG ULPI 32MLP |
| 標準包裝： | 1 |
| 系列： | * |
| 其它名稱： | FUSB2805MLXFSDKR |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
34
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
ULPI Registers
ULPI provides an immediate register set, with a 6-bit
address, that is part of the transmit command byte. An
extended register set is also provided (8-bit address)
that requires an extra clock cycle to complete. The
immediate register set is mirrored into the lower end of
the extended address space. For example, an operation
to the extended address of 00XXXXXX operates on the
immediate register set. The FUSB2805 must support
both immediate and extended register operations.
The registers specific to FUSB2805
– vendor ID,
product ID, and power control registers, are described
in the following sections.
Table 14. Register Map
Field Name
Size (bits)
Address (6 bits)
Rd
Wr
Set
Clr
Immediate Register Set
Vendor ID Low (see Table 16)
8
00h
Vendor ID High (see Table 16)
8
01h
Product ID Low (see Table 16)
8
02h
Product ID High (see Table 16)
8
03h
Function Control (see Table 17)
8
04-06h
04h
05h
06h
Interface Control (see Table 18)
8
07-09h
07h
08h
09h
OTG Control (see Table 19)
8
0A-0Ch
0Ah
0Bh
0Ch
USB Interrupt Enable Rising (see Table 20)
8
0D-0Fh
0Dh
0Eh
0Fh
USB Interrupt Enable Falling (see Table 21)
8
10-12h
10h
11h
12h
USB Interrupt Status Register (see Table 22)
8
13h
USB Interrupt Latch Register (see Table 23)
8
14h
Debug (see Table 25)
8
15h
Scratch (see Table 26)
8
16-18h
16h
17h
18h
Reserved
8
19-2Eh
Access Extended Register Set (see below)
8
2Fh
Reserved (defined in ULPI specification as vendor
specific)
8
30-3Ch
Extended Register Set
Address (8 bits)
Maps to Immediate Register Set (see below modes)
8
00-3Fh
Reserved (80-FFh defined in ULPI specification as
vendor specific)
8
40-FFh
Note:
21. 19-27h carkit; not supported by FUSB2805.
Table 15. Register Access Legend
Access Code
Expanded Name
Meaning
rd
Read
Register can be read. Read-only if this is the only mode given.
wr
Write
Pattern on the data bus is written over all bits of the register.
s
Set
Pattern on the data bus is ORd with and written into the register.
c
Clear
Pattern on the data bus is a mask. If a bit in the mask is set, the
corresponding register bit is set to zero (cleared).
Notes:
22. The register set above is compliant with the register set defined in the ULPI specifications. For details, please
refer to section 4.0 of the ULPI specifications, version 1.1.
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