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參數(shù)資料
| 型號(hào)： | FUSB2805MLX |
| 廠(chǎng)商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 40/49頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | TXRX USB2.0 HS OTG ULPI 32MLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 其它名稱(chēng)： | FUSB2805MLXFSDKR |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
45
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Dynamic Characteristics
VCC3V3= VCC-0.1 to 3.6 V; VDD1V2=1.1 V to 1.25 V; VIO=1.65 V to 3.60 V; TJ=-40°C to +85°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Output CLOCK Characteristics
fCLK60_OUT
Output Clock Frequency
Active Only When a Clock is
Input on CLKIN
60
MHz
JCLK60_OUT
RMS Output Jitter
500
ps
CLK60_OUT
Duty Cycle
50
%
tR_CLK60
Rise Time
CLOCK Pin Transitioning from
10% to 90% of VIO (CL – 4-12 pF)
1.0
4.0
ns
tF_CLK60
Fall Time
CLOCK Pin Transitioning from
90% to 10% of VIO (CL - 4-12 pF)
1.0
4.4
ns
tstartPLL
Startup (PLL Stabilization)
Time
Measured from Power Good or
Assertion of STP
640
s
Regulator Characteristics
tregPWRUP
Regulator Power-Up Time
4.7 F ±20% Decoupling on
VCC3V3 and VDD1V2
1.2
ms
tregPWRDN
Regulator Power-Down Time
4.7 F ±20% Decoupling on
VCC3V3 and VDD1V2
100
ms
Digital I/O Pins
CIN
Pin Input Capacitance
Input-only Pins, (STP, RESET_N)
2.7
3.0
3.5
pF
CIN_BIDI
Pin Input Capacitance
Bi-directional Pins as Input
(CLK, D0-D7)
2.7
3.0
3.5
pF
COUT
Pin Output Capacitance
Output (Digital) Pins (NXT, DIR,
CLKOUT)
2.7
3.0
3.5
pF
ULPI Interface Single Data Rate (SDR) Timing
tSU
Setup Time with Respect to
Positive Edge of Clock
Input-only Pins
(STP) & Bi-
directional Pins
(D0-D7) as Inputs
Output
60 MHz Clock
6
ns
tHD
Hold Time with Respect to
Positive Edge of Clock
Input-only Pins
(STP) & Bi-
directional Pins
(D0-D7) as Inputs
Output
60 MHz Clock
0
ns
tDC
Output Delay with Respect to
Positive Edge of Clock
Output-only Pins
(DIR, NXT)
Output
60 MHz
Clock, 12 pF
on all ULPI
pins
9
ns
tDD
Output Delay with Respect to
Positive Edge of Clock
Bi-directional
Pins as Output
(D0-D7)
Output
60 MHz
Clock, 12 pF
on all ULPI
pins
9
ns
trise
Rise Time
Transitioning from 10% to 90% of
VIO (CL – 4-12 pF)
1.0
5.0
ns
tfall
Fall Time
Transitioning from 90% to 10% of
VIO (CL – 4-12 pF)
1.0
5.0
ns
Continued on the following page
…
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