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參數(shù)資料
| 型號(hào)： | FUSB2805MLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 34/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX USB2.0 HS OTG ULPI 32MLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 其它名稱： | FUSB2805MLXFSDKR |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
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Functional Description
ULPI Interface Controller
The FUSB2805 provides a 12-pin interface (SDR)
compliant with the UTMI+ Low-Pin Interface (ULPI)
specification, revision 1.1. This interface must be
connected to the USB link controller.
The ULPI controller provides the following functions:
ULPI-compliant interface and register set
Full control of USB peripheral, host, and On-The-
Go functionality
Prioritizes USB receive data, USB transmit data,
interrupts, and register operations
Parses USB transmit and receive data
Controls the
VBUS external source
VBUS monitoring, charging, and discharging
Low-power mode
6- and 3-pin serial modes
Generates RX CMDs (status updates)
Maskable interrupts
Control over the ULPI bus state
USB Serializer and Deserializer
The USB data serializer prepares data for transmitting
onto the USB bus. To transmit data, the USB link
controller sends a transmit command and data on the
ULPI bus. The serializer performs parallel-to-serial
conversion, bit stuffing, and Non Return to Zero, Invert
(NRZI) encoding. For packets with a PID, the serializer
adds a SYNC pattern to the start of the packet and an
EOP pattern to the end of the packet. When the
serializer is busy and cannot accept more data, the
ULPI interface controller de-asserts NXT.
The USB data deserializer decodes data received from
the USB bus. When data is received, the deserializer
strips the SYNC and EOP patterns, if applicable, then
performs serial-to-parallel conversion, NRZI decoding,
and bit unstuffing on the data payload. The ULPI
interface controller sends the data to the USB link
controller
by
asserting
DIR,
then
asserting
NXT
whenever a byte is ready. The deserializer also detects
various
receive
errors,
including
bit-stuff
errors,
elasticity buffer under-run or over-run, and byte-
alignment errors.
USB 2.0 ATX
The USB 2.0 ATX block is an analog front-end
containing
the
circuitry
needed
for
transmitting,
receiving, and terminating the USB bus in high speed
(HS), full speed (FS), and low speed (LS); for USB
peripheral, host, and OTG implementations; per the
USB2.0 specification and its relevant supplements. The
following circuitry is included:
Differential drivers for transmitting data at HS, FS,
and LS
Differential receiver and single-ended receivers for
receiving data at HS, FS, and LS
Squelch circuit to detect HS bus activity
HS disconnect detector
45
HS bus terminations on DP and DM for
peripheral and host mode
1.5
kΩ pull-up resistor on DP for FS for peripheral
mode only (DM resistor pull up for LS peripheral is
not supported since FUSB2805 is HS capable.)
15
kΩ bus terminations on DP and DM for host
mode only
PLL and Clock Generation
The FUSB2805 has a built-in Phase Locked Loop (PLL)
for clock generation.
The PLL takes the square wave clock (19.2 MHz or
26 MHz) from the CLKIN and multiplies or divides it into
various frequencies for internal use.
From the clock source, the PLL produces the following
frequencies:
60 MHz clock for the ULPI interface controller
1.5 MHz for low-speed USB data
12 MHz for full-speed USB data
480 MHz for high-speed USB data
Interface Protection
To prevent incorrect activity when the ULPI interface is
not correctly driven by the link, such as when the link
controller powers up slower than the FUSB2805, there
is a weak pull-up resistor on the STP pin.
If the STP is unexpectedly HIGH at any time, the
FUSB2805 protects the ULPI interface by enabling
weak pull-down resistors on D[7:0].
This interface protection scheme can be disabled by
setting the INTF_PROT_DIS bit to 1b (INTF_CNTRL[7]).
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