參數(shù)資料
型號： FUSB2805MLX
廠商： Fairchild Semiconductor
文件頁數(shù)： 3/49頁
文件大?。?/td> 0K
描述： TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
11
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Table 2.
Signal Mapping on ULPI Bus During 6-Pin Serial Mode
Signal
Maps To Direction
Description
TX_ENABLE
D0
In
Active-HIGH transmit enable
TX_DATA
D1
In
Transmit the differential data on DP and DM
TX_SE0
D2
In
Transmit single-ended zero (SE0) on DP and DM
INT
D3
Out
Active-HIGH interrupt signal; asserted and latched whenever any
unmasked interrupt occurs
RX_DP
D4
Out
Single-ended receive data from DP
RX_DM
D5
Out
Single-ended receive data from DM
RX_RCV
D6
Out
Differential receive data from DP and DM
RESERVED
D7
Out
Reserved; the FUSB2805 drives this pin LOW
3-Pin FS/LS Serial Mode
This mode is provided for links that contain legacy
FS/LS
functionality
and
enables
a
cost-effective
upgrade path to HS functionality.
To enter 3-pin serial mode, the link controller sets the
3PIN_FSLS_SERIAL bit in the interface control register to
logic 1. To exit this mode, the link controller asserts STP.
An INT signal is also provided to inform the link of USB
events. If the link requires CLOCK to be running during 3-
pin serial mode, the CLK_SUSPENDM register bit must
be set to logic 1b before entering 3-pin serial mode.
The FUSB2805 requires CLKIN to be kept running when
in 3-pin mode. In 3-pin serial mode, the data bus
assignments are changed to those described in Table
3. Examples of the signaling of data packets are shown
Table 3.
Signal Mapping on ULPI Bus During 3-Pin Serial Mode
Signal
Maps To
Direction
Description
TX_ENABLE
D0
In
Active-HIGH transmit enable
DAT
D1
I/O
Transmit differential data on DP and DM when TX_ENABLE is HIGH
Receive differential data from DP and DM when TX_ENABLE is LOW
SE0
D2
I/O
Transmit single-ended zero on DP and DM when TX_ENABLE is HIGH
Receive single-ended zero on DP and DM when TX_ENABLE is LOW
INT
D3
Out
Active-HIGH interrupt signal; asserted and latched whenever any
unmasked interrupt occurs
RESERVED
D[7:4]
Out
Reserved; the FUSB2805 drives this pin LOW
Power Supply Modes
The FUSB2805 supports two basic modes of supply
operation and include the following:
Normal Mode
Power-Down Mode
Normal Mode
This mode is entered when VCC and VIO are powered
and Chip_Select_N is asserted.
Power-Down Mode
When chip select is inactive, FUSB2805 enters power-
down mode, during which the following apply:
Chip_Select_N is HIGH or VIO is not present.
All internal circuits are powered down; total VCC
current <36 A.
D[0-7], CLOCK, NXT, and DIR are three-stated and
ignored; STP is ignored.
Voltage regulators powering the OTG PHY are
turned off.
Pull-down resistors on the ULPI interface are
enabled to prevent a floating bus (VIO present).
The FUSB2805 is forced into a low-power state
and ignores any ULPI commands, including
wake-up events.
If VIO is not present, those signals referenced to VIO
are also not powered.
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