參數(shù)資料
型號(hào)： FUSB2805MLX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 48/49頁(yè)
文件大?。?/td> 0K
描述： TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱(chēng)： FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
8
F
USB2
8
0
5
—
USB2
.0
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VCC
VCC is the main input supply voltage for FUSB2805. The
FUSB2805 operates correctly when VCC is between
2.7 V and 4.5 V. The maximum transients that should
be seen on VCC are 5.5V for a maximum of 5ms. A
100nF decoupling capacitor is preferred.
PSW
This is an active-HIGH, open-source, power-switch
analog output. This pin can be connected to an external
VBUS switch or an external charge pump enable circuit
to control the external
VBUS power source. If the link
controller is in host mode, this can be set via the
DRV_VBUS and DRV_VBUS_EXT bits in the OTG
control register to logic 1. The FUSB2805 drives PSW
to HIGH to enable the external VBUS supply. If the link
controller
detects
an
over-current
condition
(VBUS_valid=0), it should disable the external VBUS supply
by setting DRV_VBUS_EXT to 0b. An external 100 k
pull-down resistor is used.
In addition, the polarity of the signal that controls PSW
can be changed via the INTF_CTRL register.
VBUS
This power I/O pin acts as input to the
VBUS
comparators and over-current detector.
When the DRIVE_VBUS bit of the OTG control register
is set to 1b, an external
VBUS source tries to drive VBUS
to a voltage of 4.4 V to 5.25 V with an output current
capability of at least 8 mA.
VCC3V3 and VDD1V2
Regulator output voltages. These supplies are used to
internally power digital and analog circuits.
CLKIN
Clock input pin; CLKIN is the digital clock input. The
allowed frequencies on CLKIN are 19.2 MHz and
26 MHz. The frequency tolerance required by the clock
is 50 ppm. The link controller requires a 60 MHz clock
from the FUSB2805. This is generated from the PLL,
which uses the CLKIN as the input clock.
19.2 MHz
– CFG1 set to LOW
26 MHz
– CFG1 set to HIGH
CHIP SELECT_N
Active LOW chip-select pin. When asserted HIGH; D[0-
7], CLOCK, DIR, and NXT pins are three-stated and
ignored and all internal circuits are powered down,
including the regulator. When LOW, the FUSB2805
wakes up and the ULPI pins operate normally.
IR
Direction output pin. This pin is synchronous to the
rising edge of CLOCK and controls the direction of the
data bus. By default, the FUSB2805 holds DIR LOW,
causing the data bus to be an input. When DIR is LOW,
the FUSB2805 listens for data from the link controller.
The FUSB2805 pulls DIR HIGH only when it has data to
send to the link, which is for one of two reasons:
1.
To send USB receive data, RX CMD status updates,
and register-read data to the link controller.
2.
To block the link controller from driving the data
bus during power up, reset, and low-power mode
(suspend).
The
DIR
pin
can
also
be
three-stated
when
Chip_Select_N is de-asserted HIGH .
STP
Stop input pin. This signal is synchronous to the rising
edge of CLOCK. The link must assert STP to signal the
end of a transmit packet or a register-write operation.
When DIR is asserted, the link controller can optionally
assert STP to abort the FUSB2805, causing it to de-
assert DIR in the next clock cycle.
NXT
Next data output pin. This signal is synchronous to the
rising edge of CLOCK. The FUSB2805 holds NXT LOW
by default. When DIR is LOW and the link is sending
data, NXT is asserted to tell the link to provide the next
data byte. When DIR is HIGH and the FUSB2805 is
sending data to the link, NXT is asserted to tell the link
another valid byte is on the bus. NXT is not used for
register read data or the RX CMD status update.
The
NXT
pin
can
also
be
three-stated
when
Chip_Select_N is de-asserted HIGH.
CLOCK
This is the 60MHz interface clock for synchronizing the
ULPI bus. It is configured as an output. Being a 12-pin
interface implementation, all the ULPI signals are
synchronous to the rising edge of CLOCK. The
FUSB2805 accepts a digital clock input and outputs the
60MHz to the link.
GND
The global ground signal acts as a ground to all circuits
in the FUSB2805.
Reset_N
Reset_N is an active LOW reset signal with VIO voltage.
Tie to VIO 1.8 V if not used. Typically tied to the power-
on reset signal of the product.
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