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參數(shù)資料
| 型號(hào)： | FUSB2805MLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 33/49頁 |
| 文件大小： | 0K |
| 描述： | TXRX USB2.0 HS OTG ULPI 32MLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 其它名稱： | FUSB2805MLXFSDKR |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
39
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
USB Interrupt Status Register
– USB_INTR_STAT (13h Read Only)
These register bits indicate the current value of the
interrupt event source signal. Interrupt circuitry can be
powered down in any mode when both rising and falling
edge enables are disabled. To ensure interrupts are
detectable when CLOCK is powered down, the link
should enable both rising and falling edges.
Table 22. USB Interrupt Status Register
Field Name
Bits
Access
Reset
Description
HostDisconnect
0
rd
0b
Current value of UTMI+ HostDisconnect output. Applicable only in
host mode (DpPulldown and DmPulldown both set to 1b).
Automatically reset to 0b when low-power mode is entered.
VBUSValid
1
rd
0b
Current value of UTMI+ VBUSValid output.
SessValid
2
rd
0b
Current value of UTMI+ SessValid output. SessValid is the same as
UTMI+ AValid.
SessEnd
3
rd
0b
Current value of UTMI+ SessEnd output.
IDGnd
4
rd
0b
Current value of UTMI+ IDGnd output. IDGnd is valid 50ms after
IDPullup is set to 1b; otherwise, IDGnd is undefined and should be
ignored.
RESERVED
7:5
rd
Xb
Reserved
USB Interrupt Latch
– USB_INTR_L (14h Read Only with Auto-Clear)
These register bits are set by the FUSB2805 when an
unmasked change occurs on the corresponding internal
signal. The FUSB2805 automatically clears all bits
when the link reads this register or when low-power
mode is entered. The FUSB2805 also clears this
register when either 6-pin or 3-pin serial mode is
entered, regardless of the value of ClockSuspendM.
Interrupt circuitry can be powered down in any mode
when both rising and falling edge enables are disabled.
To ensure interrupts are detectable when CLOCK is
powered down, the link should enable both rising and
falling edges.
It is optional for the link to read the USB Interrupt Latch
register in synchronous mode because the RXCMD
byte already indicates the interrupt source directly.
Table 23. USB Interrupt Latch Register
Field Name
Bits
Access
Reset
Description
HostDisconnect Latch
0
rd
0b
Set to 1b by the FUSB2805 when an unmasked event occurs
on HostDisconnect. Cleared when this register is read.
Applicable only in host mode (DpPulldown and DmPulldown
both set to 1b).
VBUSValid Latch
1
rd
0b
Set to 1b by the FUSB2805 when an unmasked event occurs
on VBUSValid. Cleared when this register is read.
SessValid Latch
2
rd
0b
Set to 1b by the FUSB2805 when an unmasked event occurs
on SessValid. Cleared when this register is read. SessValid is
the same as UTMI+ AValid.
SessEnd Latch
3
rd
0b
Set to 1b by the FUSB2805 when an unmasked event occurs
on SessEnd. Cleared when this register is read.
IDGnd Latch
4
rd
0b
Set to 1b by the FUSB2805 when an unmasked event occurs
on IDGnd. Cleared when this register is read. IDGnd is valid
50 ms after IDPullup is set to 1b; otherwise, IDGnd is undefined
and should be ignored.
RESERVED
7:5
rd
0b
Reserved
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