參數(shù)資料
型號： FUSB2805MLX
廠商： Fairchild Semiconductor
文件頁數(shù)： 39/49頁
文件大?。?/td> 0K
描述： TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
44
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Static Characteristics (Continued)
VCC3V3= VCC-0.1 to 3.6 V; VDD1V2=1.1 V to 1.25 V; VIO=1.65 V to 3.60 V; TJ=-40°C to +85°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VBUS Resistors
RVBUS(PU)
VBUS Charge Resistance
Connect to VCC3V3 when
CHRG_VBUS=1
281
RVBUS(PD)
VBUS Discharge Resistance
Connect to GND when
DISCHRG_VBUS=1
656
RVBUS(IDLE)
VBUS Idle Impedance
Not in Power-Down Mode
80
90
100
k
Chip Select De-assserted
or VIO Lost
40
100
ID Detection Circuit (ID)
tID
ID Detection Time
50
ms
RID_PU
ID Pull-Up Resistance
Bit ID_PULL_UP=1
40
50
60
k
RID_PU_WK
Weak ID Pull-Up Resistance
Bit ID_PULL_UP=0
320
400
480
k
VPU_ID
ID Pull-Up Reference
3.0
3.3
3.6
V
VTH_ID
ID Threshold
1.0
2.0
V
External Resistor Reference
VRREF
Voltage Across External RREF
(12
kΩ ±1%)
SUSPENDM Bit=HIGH
0.8
V
Reset
tSTART_HOST
PHY Clock Startup when Remote
Wake-up Event Occurs
CLKIN Running,
Autoresume=0
850
s
CLKIN Must be Started
First
(30), Autoresume=1
110.9
s
Clock Input
fCLKIN
Input Clock Frequency
USB Config 0
19.2
MHz
USB Config 1
26.0
JCLKIN
RMS Jitter
200
ps
CLKIN
Duty Cycle
50
%
VCLKIN
Amplitude
1.8
V
tR_CLKIN,
tF_CLKIN
Rise and Fall Time
5
ns
Output CLOCK Characteristics
fCLK60_OUT
Output Clock Frequency
Active Only When a Clock
is Input on CLKIN
60
MHz
JCLK60_OUT
RMS Output Jitter
500
ps
CLK60_OUT
Duty Cycle
50
%
tR_CLK60
Rise Time
CLOCK Pin Transitioning
from 10% to 90% of VIO
(CL 4 – 12 pF)
1.0
4.0
ns
tF_CLK60
Fall Time
CLOCK Pin Transitioning
from 90% to 10% of VIO
(CL 4 – 12 pF)
1.0
4.4
ns
tstartPLL
Startup (PLL Stabilization) Time
Measured from Power
Good or Assertion of STP
640
s
Notes:
29. Excludes suspend current through 15 k
host pull-down when configured as a peripheral controller. Typically an
additional 200 A is allowed.
30. Time for CLKIN to be woken up is a function of external system timing, so Autoresume is needed for remote
wake-up capability (please see Figure 18).
31. An external clock is to be applied to the CLKIN pin. Recommended frequency accuracy is 200 ppm.
相關(guān)PDF資料
PDF描述
FXLA2203UMX TRANSLATOR LEVEL DUAL 24UMLP
GAL16V8D-15LJN SPLD 62.5MHZ EECMOS 20 PLCC
GAL18V10B-20LP IC GAL 10OUT MACROCELL 7.5NS 20
GAL22V10D-25LJ IC SPLD 3.3V 28-PLCC
GH65C11-C-PD OPTO ENCODER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FUSCA REF BOARD 制造商:TDK 功能描述:REFERENCE BOARD FUSCA 2.4GHZ
FUSCAREFBOARD 制造商:Antenova 功能描述:Reference Board Fusca 2.4GHz
FUSE 功能描述:保險絲 Fuse, Fiber 20A 600V Lot Qty 5 RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險絲類型:Fast Acting 保險絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485
FUSE 25A ATC 制造商:American Technical Ceramics Corp 功能描述: 制造商:ATC 功能描述:
FUSE KIT D 制造商:COOPER BUSSMANN 功能描述:BUSSMANN FUSE KIT
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*