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參數(shù)資料
| 型號： | FUSB2805MLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 9/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX USB2.0 HS OTG ULPI 32MLP |
| 標準包裝： | 1 |
| 系列： | * |
| 其它名稱： | FUSB2805MLXFSDKR |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
17
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
USB Packet Timing
The USB2.0 specification defines the inter-packet
timing
and
the
UTMI/UTMI+
specifications
define
synchronization and processing delays. The ULPI Rev.
1.1 specification defines the inter-packet delays to
ensure compatibility with USB2.0 and supplemental
specifications.
Pipeline Delays
Table 6 describes the delays (in clock cycles) with
which to comply using ULPI. The USB bus events are
measured relative to D+ and D-. The ULPI timings are
relative to the clock edge on which the transition is
detected (i.e. the clock edge on which STP is detected).
Table 6.
Pipeline Delays
Parameter Name
HS PHY
Delay
FS PHY
Delay
LS PHY
Delay
Definition
RXCMD Delay(J/K)
4
Number of clocks after a change in the internal
USB bus state is detected to an RXCMD byte being
sent over the ULPI bus. Applies to all changes
except SE0.
RXCMD Delay(SE0)
4
4 to 6
16 to 18
Number of clocks between the USB bus state
indicating SE0 to an RXCMD byte being sent over
the ULPI bus. Delay is increased due to filtering.
TX Start Delay
1 to 2
6 to 10
74 to 75
Number of clocks between the FUSB2805 detecting
a TXCMD on the ULPI bus to transmitting the first K
of the SYNC pattern on the USB bus.
TX End Delay (packets)
2 to 5
NA
Number of clocks between the FUSB2805 detecting
STP on the ULPI bus to completing EOP
transmission on the USB bus.
HS EOP is completed when all eight consecutive
ones have finished transmitting on the USB bus.
FS/LS packets finish many clock cycles after STP
is asserted. The link must look for RXCMD bytes
indicating SE0-to-J transition to determine when the
transmission is completed on the USB bus.
TX End Delay (SOF)
6 to 9
NA
HS SOF packets have a long EOP. The link must
wait at least nine clocks or for an RXCMD,
indicating squelch (LINESTATE=00b), before
transmitting the next packet.
RX Start Delay
3 to 8
NA
Number of clocks after first K of SYNC pattern is
seen on the USB bus to the simultaneous assertion
of DIR and NXT or an RXCMD indicating RxActive.
Used for HS packets only.
For FS/LS packets, the link must look for RXCMD
bytes indicating J-to-K transition.
RX End Delay
3 to 8
17 to 18
122 to 123
Number of clocks after EOP occurs on the USB bus
to the FUSB2805 de-asserting DIR or indicating
RxActive LOW in an RXCMD byte.
HS EOP is completed when all eight consecutive
ones have finished transmitting on the USB bus.
FS/LS EOP occurs when SE0 starts on the USB
bus. For FS/LS, the link uses LINESTATE and not
RxEnd delay to time USB packets.
Note:
11. Please refer to ULPI Rev 1.1 specifications, section 3.8.2.6.2 for details on PHY pipeline delays.
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