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參數(shù)資料
| 型號： | HY5PS12423LF |
| 英文描述： | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 128Mx4 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M |
| 文件頁數(shù)： | 22/66頁 |
| 文件大?。?/td> | 862K |
| 代理商： | HY5PS12423LF |
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Rev. 0.52/Nov. 02 22
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR-II SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ,
and finally to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up,
which may cause permanent damage to the device. VREF can be applied any time after VDDQ, but is
expected to be nominally coincident with VTT. The DQ and DQS outputs are in the High-Z state, where they
remain until driven active in normal operation (by a read access). After all power supply, reference voltages,
and the clocks are stable, the DDR-II SDRAM requires a 200us delay prior to applying an executable command.
Once the 200us delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be
brought HIGH. Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register
Set command must be issued for the Extended Mode Register, to enable the DLL. Then a Mode Register
Set command must be issued for the Mode Register, to reset the DLL and to program the operating
parameters. 200 clock cycles are required between the DLL reset and any read command. A Precharge ALL
command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two Auto Refresh cycles must be performed. Additionally, a Mode Register Set command
for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without
resetting the DLL) must be performed. Following these cycles, the DDR-II SDRAM is ready for normal operation.
Failure to follow these steps may lead to unpredictable start-up modes.
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE and ODT
at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock(CK, CK), apply NOP & take CKE high.
4. Wait tRFC
then issue precharge commands for all banks of the device.
5. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and
"Low" to all of the rest address pins, A1~A11 and BA1)
6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to
lock the DLL.
(To issue DLL reset command, provide "High" to A8 and "Low" to BA0)
7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
10. Carry out OCD (Off Chip Driver impedance adjustment). At Least, EMRS OCD Default command
(A9=A8=A7=1) must be issued.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5PS12823F | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823LF | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5P | Current Transducers HY 5 to 25-P/SP1 |
| HY5R256HC | -|2.5V|8K|40|Direct RDRAM - 256M |
| HY5R288HC | -|2.5V|8K|40|Direct RDRAM - 288M |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS12821AF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-C3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AFP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
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