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參數(shù)資料
| 型號(hào)： | HY5PS12423LF |
| 英文描述： | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 128Mx4 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M |
| 文件頁數(shù)： | 50/66頁 |
| 文件大小： | 862K |
| 代理商： | HY5PS12423LF |
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Rev. 0.52/Nov. 02 50
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Auto Precharge
The auto precharge command is issued in conjunction with a specific read or write command. If read or write with
auto precharge is issued, precharge command is performed automatically upon completion of the read or write burst.
Therefore, activatied bank is closed/ precharged without precharge command. Either normal read (or write) or read
(or write) with auto precharge is determined by A10. If A10 is low when read (or write) command is issued, DRAM
remain row active state after read or write burst operation. If A10 is high when read (or write) command is issued,
DRAM perform read (or write) with auto precharge.
If read with auto precharge is issued to DRAM, DRAM execute normal read burst and then, begin to precharge on the
rising edge which is CAS latency (CL) clock cycles before the end of the read burst. If write with auto precharge is
issued to DRAM, DRAM execute normal write burst and then, begin to precharge after data-in burst is properly stored
The RAS lock-out circuit internally delays the Precharge operation until the array restore operation has been completed
so that the auto precharge command may be issued with any read or write command.
This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent
upon CAS latency) thus improving system performance for random data access. The RAS lock-out circuit internally
delays the Precharge operation until the array restore operation has been completed so that the auto precharge com-
mand may be issued with any read or write command.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5PS12823F | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823LF | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5P | Current Transducers HY 5 to 25-P/SP1 |
| HY5R256HC | -|2.5V|8K|40|Direct RDRAM - 256M |
| HY5R288HC | -|2.5V|8K|40|Direct RDRAM - 288M |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS12821AF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-C3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AFP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
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