參數(shù)資料
型號: HY5PS12423LF
英文描述: 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述: 128Mx4 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M
文件頁數(shù): 24/66頁
文件大小: 862K
代理商: HY5PS12423LF
Rev. 0.52/Nov. 02 24
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of RAS, CAS, CS, WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. The mode register set com-
mand time(tMRD) must be satisfied to write the data in mode register. During the MRS cycle, any command cannot be
issued. Once mode register field is determined, the information will be held until resetted by another MRS command.
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
tWR
DR
TM
CAS Latency
BT
Burst Length
A2
A1
A0
Burst Length
Sequential
Interleave
0
0
0
Reserved
Reserved
0
0
1
Reserved
Reserved
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
A3
Burst Type
0
Nibble Sequential
1
Interleave
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2(optional)
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
Reserved
1
1
1
Reserved
A7
Test Mode
0
Normal
1
Vendor
test mode
A8
DLL Reset
0
No
1
Yes
BA0
MRS Type
0
MRS
1
EMRS
A11
A10
A9
tWR
0
0
0
Disable
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
Reserved
1
1
1
Reserved
相關(guān)PDF資料
PDF描述
HY5PS12823F 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12823LF 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5P Current Transducers HY 5 to 25-P/SP1
HY5R256HC -|2.5V|8K|40|Direct RDRAM - 256M
HY5R288HC -|2.5V|8K|40|Direct RDRAM - 288M
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