參數(shù)資料
型號(hào): HY5PS12423LF
英文描述: 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述: 128Mx4 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M
文件頁數(shù): 55/66頁
文件大?。?/td> 862K
代理商: HY5PS12423LF
Rev. 0.52/Nov. 02 55
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Self Refresh
When auto refresh command with CKE=low is issued, DDR-II DRAM entered self refresh mode. During the self refresh
mode, DRAM retain data without external clocking and any external system control. Before issuing Self Refresh com-
mand, all banks must be in a precharge state and CKE must be low. All input buffer is turned off except CKE pin,
which means all input signals (except CKE) are Don’t care during self refresh. On-chip DLL is automatically disabled
upon entering self refresh mode. DRAM retains data by internal self refresh operation. Self refresh mode is exit by
assering CKE high. Once CKE is high, the DDR II SDRAM must have NOP commands issued for tXSNR because time is
required for the completion of any internal refresh in progress. After self refresh exit, stable input clock should be sup-
plied to DRAM. A minimum of 200 cycles of stable input clock, where CKE is held high, is required to lock the internal
DLL circuit of DDR-II SDRAM.
/CK
CK
CKE
Self Refresh
CMD
NOP
Non Read
Enter self refresh mode
Exit Self Refresh mode
Read
tXSNR
~
tXSNR
~
~
~
~
~
~
~
相關(guān)PDF資料
PDF描述
HY5PS12823F 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12823LF 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5P Current Transducers HY 5 to 25-P/SP1
HY5R256HC -|2.5V|8K|40|Direct RDRAM - 256M
HY5R288HC -|2.5V|8K|40|Direct RDRAM - 288M
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