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參數(shù)資料
| 型號： | HYB 39S256160CT |
| 廠商： | SIEMENS AG |
| 英文描述： | 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動態(tài)RAM) |
| 中文描述： | 256兆位（4banks ×的4Mb × 16）同步DRAM（256M（4列× 4分位× 16）同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 11/41頁 |
| 文件大?。?/td> | 327K |
| 代理商： | HYB 39S256160CT |
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INFINEON Technologies
11
1.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations
are possible. With the programmed burst length, alternate access and precharge operations on two
or more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages.
Burst Length and Sequence
:
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the
CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying
any refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE
are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the
word lines after RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control
signals including the clock are disabled. Returning CKE to high enables the clock and initiates the
refresh exit operation. After the exit command, at least one tRC delay is required prior to any access
command.
DQM Function
Burst
Length
Starting Address
(A2 A1 A0)
Sequential Burst Addressing
(decimal)
Interleave Burst Addressing
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4
x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8
000
001
010
011
100
101
110
111
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB 39S64160AT | 4M x 16 MBit Synchronous DRAM for High Speed Graphics Applications(64M位(4M x 16)同步動態(tài)RAM（用于高速圖形場合）) |
| HYB 39S64160BT | 4M x 16 MBit Synchronous DRAM for High Speed Graphics Applications(64M位(4列 × 1M位 × 16)同步動態(tài)RAM（用于高速圖形場合）) |
| HYB 39S64400BT | 64MBit Synchronous DRAM(64M位(4列 × 4M位 × 4)同步動態(tài)RAM) |
| HYB 39S64800BT | 64MBit Synchronous DRAM(64M位(4列 × 2M位 × 8)同步動態(tài)RAM) |
| HYB 39S64XXX0BTL | 64MBitSynchronous DRAM(64M位同步動態(tài)RAM(低功耗版)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S256160CT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S256160CT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mb (16M x 16) PC100 2-2-2? |
| HYB39S256160CT-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S256160CTL-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S256160CTL-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
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