參數(shù)資料
型號: HYB 39S256160CT
廠商: SIEMENS AG
英文描述: 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動態(tài)RAM)
中文描述: 256兆位(4banks ×的4Mb × 16)同步DRAM(256M(4列× 4分位× 16)同步動態(tài)RAM)的
文件頁數(shù): 18/41頁
文件大?。?/td> 327K
代理商: HYB 39S256160CT
INFINEON Technologies
18
1.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests have V
il
= 0.4 V and V
ih
= 2.4 V with the timing referenced to the 1.4 V crossover point. The
transition time is meas ured between V
ih
and V
il
. All AC measurements assume t
T
=1ns with the AC output load
circuit shown in fig.1.Specified tac and toh parameters are measured with a 50 pF only, without any resistive
termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (t
T
/2 - 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (t
T
-1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock,
as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit
command is registered.
6. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
fig.1
50 pF
I/O
Measurement conditions for
tac and toh
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
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