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參數(shù)資料
| 型號： | HYB 39S256160CT |
| 廠商： | SIEMENS AG |
| 英文描述： | 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動態(tài)RAM) |
| 中文描述： | 256兆位（4banks ×的4Mb × 16）同步DRAM（256M（4列× 4分位× 16）同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 12/41頁 |
| 文件大?。?/td> | 327K |
| 代理商： | HYB 39S256160CT |
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INFINEON Technologies
12
1.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
DQM has two functions for data I/O read and write operations. During reads, when it turns to
high“ at a clock timing, data outputs are disabled and become high impedance after two clock delay
(DQM Data Disable Latency t
DQZ
). It also provides a data mask function for writes. When DQM is
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency t
DQW
= zero
clocks).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks
must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can
enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the
receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any
refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh
period (tref) of the device. Exit from this mode is performed by taking CKE high“. One clock delay
is required for power down mode entry and and two clocks exit.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the
Read with Auto-Precharge
function is initiated. If CA10 is high when a Write Command is issued, the
Write with Auto-
Precharge
function is initiated. The SDRAM automatically enters the precharge operation a time
delay equal to t
WR
(“write recovery time”) after the last data in.
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS
latency = 3. Writes require a time delay twr (“write recovery time”) of 2 clocks minimum from the last
data out to apply the precharge command.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB 39S64160AT | 4M x 16 MBit Synchronous DRAM for High Speed Graphics Applications(64M位(4M x 16)同步動態(tài)RAM（用于高速圖形場合）) |
| HYB 39S64160BT | 4M x 16 MBit Synchronous DRAM for High Speed Graphics Applications(64M位(4列 × 1M位 × 16)同步動態(tài)RAM（用于高速圖形場合）) |
| HYB 39S64400BT | 64MBit Synchronous DRAM(64M位(4列 × 4M位 × 4)同步動態(tài)RAM) |
| HYB 39S64800BT | 64MBit Synchronous DRAM(64M位(4列 × 2M位 × 8)同步動態(tài)RAM) |
| HYB 39S64XXX0BTL | 64MBitSynchronous DRAM(64M位同步動態(tài)RAM(低功耗版)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S256160CT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S256160CT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mb (16M x 16) PC100 2-2-2? |
| HYB39S256160CT-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S256160CTL-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S256160CTL-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
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