- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370792 > HYB39S256800 (SIEMENS AG) 256 MBit Synchronous DRAM(256M位同步動(dòng)態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | HYB39S256800 |
| 廠商： | SIEMENS AG |
| 英文描述： | 256 MBit Synchronous DRAM(256M位同步動(dòng)態(tài)RAM) |
| 中文描述： | 256兆比特同步DRAM（256M位同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 10/46頁 |
| 文件大小： | 594K |
| 代理商： | HYB39S256800 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
INFINEON Technologies
10
HYB39S256400/800/160T
256MBit Synchronous DRAM
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined.
The following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200
μ
s is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is
divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit
to program the column access sequence in a burst cycle (interleaved or sequential), a CAS
Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between
normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The
mode set operation must be done before any activate command after the initial power up. Any
content of the mode register can be altered by re-executing the mode set command. All banks must
be in precharged state and CKE must be high at least one clock before the mode set operation. After
the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and
WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, t
RCD
, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read
or write operations are allowed at up to a 143 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8. Column addresses are
segmented by the burst length and serial data accesses are done within this boundary. The first
column address to be accessed is supplied at the CAS timing and the subsequent addresses are
generated automatically by the programmed burst length and its sequence. For example, in a burst
length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is
3, 0, 1, 6, 7, 4, and 5.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB39S256400DC-6 | 256 MBit Synchronous DRAM |
| HYB39S256400DC-7 | 256 MBit Synchronous DRAM |
| HYB39S256400DC-75 | Polypropylene metallized tape wrap and epoxy filled - Snubber |
| HYB39S256400DC-8 | 256 MBit Synchronous DRAM |
| HYB39S256400DCL-7 | 256 MBit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S256800AT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HYB39S256800AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HYB39S256800AT-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HYB39S256800AT-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HYB39S256800CT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mb (32M x 8) PC133 3-3-3? |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。