參數(shù)資料
型號(hào)： HYB39S256800
廠商： SIEMENS AG
英文描述： 256 MBit Synchronous DRAM(256M位同步動(dòng)態(tài)RAM)
中文描述： 256兆比特同步DRAM（256M位同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 18/46頁(yè)
文件大?。?/td> 594K
代理商： HYB39S256800
INFINEON Technologies
18
HYB39S256400/800/160T
256MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have V
il
= 0.4 V and V
ih
= 2.4 V with the timing referenced to the 1.4 V
crossover point. The transition time is meas ured between V
ih
and V
il
. All AC measurements assume t
T
=1ns
with the AC output load circuit shown in fig.1.Specified tac and toh parameters are measured with a 50 pF only,
without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (t
T
/2 - 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (t
T
-1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock,
as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit
command is registered.
1.5V
1.5V
tSETUP
tHOLD
tAC
tAC
tLZ
tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.5 V
50 Ohm
2.4 V
0.4 V
t
T
fig.1
tCH
tCL
50 pF
I/O
Measurement conditions for
tac and toh
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB39S256800AT-7.5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM
HYB39S256800AT-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM
HYB39S256800AT-8A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM
HYB39S256800AT-8B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM
HYB39S256800CT-7.5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mb (32M x 8) PC133 3-3-3?
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