參數(shù)資料
型號: IDT5V9888PFGI8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 500 MHz, OTHER CLOCK GENERATOR, PQFP32
封裝: GREEN, TQFP-32
文件頁數(shù): 1/37頁
文件大小: 354K
代理商: IDT5V9888PFGI8
1
INDUSTRIALTEMPERATURERANGE
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
AUGUST 2006
2006 Integrated Device Technology, Inc.
DSC 7044/8
c
IDT5V9888
ADVANCE
INFORMATION
INDUSTRIAL TEMPERATURE RANGE
3.3V EEPROM
PROGRAMMABLE CLOCK
GENERATOR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Three internal PLLs
Internal non-volatile EEPROM
JTAG and FAST mode I2C serial interfaces
Input Frequency Ranges: 1MHz to 400MHz
Output Frequency Ranges: 4.9kHz to 500MHz
Reference Crystal Input with programmable oscillator gain and
programmable linear load capacitance
Crystal Frequency Range: 8MHz to 50MHz
Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
10-bit post-divider blocks
Fractional Dividers
Two of the PLLs support Spread Spectrum Generation
capability
I/O Standards:
Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
Inputs - 3.3V LVTTL/ LVCMOS
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Redundant clock inputs with glitchless auto and manual
switchover options
JTAG Boundary Scan
Individual output enable/disable
Power-down mode
3.3VVDD
Available in TQFP and VFQFPN packages
DESCRIPTION:
The IDT5V9888 is a programmable clock generator intended for high
performance data-communications, telecommunications, consumer, and
networking applications. There are three internal PLLs, each individually
programmable, allowing for three unique non-integer-related frequencies.
The frequencies are generated from a single reference clock. The
reference clock can come from one of the two redundant clock inputs. A
glitchless automatic or manual switchover function allows any one of the
redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG
interfaces. The programming interface enables the device to be pro-
grammed when it is in normal operation or what is commonly known as in-
system programmable. An internal EEPROM allows the user to save and
restore the configuration of the device without having to reprogram it on
power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback
divider. This allows the user to generate three unique non-integer-related
frequencies. The PLL loop bandwidth is programmable to allow the user
totailorthePLLresponsetotheapplication. Forinstance,theusercantune
the PLL parameters to minimize jitter generation or to maximize jitter
attenuation. Spread spectrum generation and fractional divides are
allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The
other four output banks are LVTTL. The outputs are connected to the PLLs
via the switch matrix. The switch matrix allows the user to route the PLL
outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize
the board layout. In addition, each output's slew rate and enable/disable
function can be programmed.
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