- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67712 > IDT5V9888PFGI8 (INTEGRATED DEVICE TECHNOLOGY INC) 500 MHz, OTHER CLOCK GENERATOR, PQFP32 PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT5V9888PFGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 17/37頁 |
| 文件大小： | 354K |
| 代理商： | IDT5V9888PFGI8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
24
INDUSTRIALTEMPERATURERANGE
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
EEPROMINTERFACE
The IDT5V9888 can also store its configuration in an internal EEPROM. The contents of the device's internal programming registers can be saved to the
EEPROMbyissuingasaveinstruction(ProgSave)andassertingtheWRITEENABLEpinLOW. Theycanbeloadedbacktotheinternalprogrammingregisters
by issuing a restore instruction (ProgRestore).
ToinitiateasaveorrestoreusingI2C,onlytwobytesaretransferred.TheDeviceAddressisissuedwiththeread/writebitsetto"0",followedbytheappropriate
commandcode.ThesaveorrestoreinstructionexecutesaftertheSTOPconditionisissuedbytheMaster,duringwhichtimetheIDT5V9888willnotgenerate
Acknowledgebits. The5V9888willacknowledgetheinstructionsafterithascompletedexecutionofthem. Duringthattime,theI2Cbusshouldbeinterpreted
as busy by all other users of the bus.
UsingJTAG,theProgSaveandProgRestoreinstructionsselectstheBYPASSregisterpathforshiftingthedatafromTDItoTDOduringthedataregisterscanning.
During the execution of a ProgSave or ProgRestore instruction, the IDT5V9888 will not accept a new programming instruction (read, write, save, or restore).
Allnon-programmingJTAGinstructionswillfunctionproperly,buttheusershouldwaituntilthesaveorrestoreiscompletebeforeissuinganewprogramming
instruction. Ifanewprogramminginstructionisissuedbeforethesaveorrestorecompletes,thenewinstructionisignored,andtheBYPASSregisterpathremains
ineffectforshiftingdatafromTDItoTDOduringdataregisterscanning.
The time it takes for the save (TSAVE) and restore (TRESTORE) instructions to complete can be calculated as follows:
TSAVE/TRESTORE = 128 bytes * 8 bits/byte * 1/300KHz + overhead (ms)
ThewaittimebeforeassertingtheWRITEENABLEpinafterthecompletionofasaveinstructionisaminimumof10ms.
PROGSAVE
To save configuration into EEPROM, WRITE ENABLE pin must be set LOW
PROGRESTORE
NOTE:
PROGWRITE is for writing to the 5V9888 registers.
PROGREAD is for reading the 5V9888 registers.
PROGSAVE is for saving all the contents of the 5V9888 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the 5V9888 registers.
S
Address
R/W
ACK
Command Code ACK
7-bits
0
1-bit
8-bits:xxxxxx01
1-bit
P
S
Address
R/W
ACK
Command Code ACK
7-bits
0
1-bit
8-bits:xxxxxx10
1-bit
P
JTAGINTERFACE
InadditiontotheIEEE1149.1instructionsEXTEST,SAMPLE/PRELOAD,
CLAMP, HIGH-Z and BYPASS, the 5V9888 allows access to internal
programmingregistersusingtheREGADDR(setregisteraddress),REGDATAR
(read register) and REGDATW (write register instructions. Data is always
accessedbybyte,andtheregisteraddressincrementsaftereachreadorwrite.
Thefullinstructionsetfollows. TheIDT5V9888willbeupdatingtheregisters
duringprogramming.
The JTAG TAP controller can be reset in one of four ways:
1) Power up in JTAG mode
2) PowerupinI2CmodeandthengointoJTAGmode,orgooutofandback
into JTAG mode with the I2C/JTAG pin
3) Apply TRST while in JTAG mode
4) Apply five rising edges of TCK with TMS high while in JTAG mode
IR (3)
IR (2)
IR (1)
IR (0)
Instructions
0
EXTEST(1)
0
1
SAMPLE/PRELOAD(1)
0
1
0
IDCODE(1)
0
1
REGADDR(2)
0
1
0
REGDATAW / PROGWRITE(3)
0
1
0
1
REGDATAR / PROGREAD(4)
0
1
0
PROGSAVE(5)
0
1
PROGRESTORE(6)
1
0
CLAMP(1)
1
0
1
HIGHZ(1,7)
1
BYPASS(1)
JTAG INSTRUCTION REGISTER
DESCRIPTION
NOTES:
1. IEEE 1149.1 definition
2. REGADDR is for setting a specific 5V9888 register address.
3. REGDATAW/PROGWRITE is for writing to the 5V9888 registers.
4. REGDATAR/PROGREAD is for reading the 5V9888 registers.
5. PROGSAVE is for saving all the contents of the 5V9888 registers to the EEPROM.
WRITE ENABLE pin must be asserted LOW.
6. PROGRESTORE is for loading the entire EEPROM contents to the 5V9888 registers.
7. The OEMs bits for OUT1-6 must be set for tri-state when using the HIGHZ instruction
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT5V9888PFGI | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| IDT5V9955BFGI | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA96 |
| IDT7216L20J8 | 16-BIT, DSP-MULTIPLIER, PQCC68 |
| IDT7216L25PQF | 16-BIT, DSP-MULTIPLIER, PQFP64 |
| IDT7216L45PQF | 16-BIT, DSP-MULTIPLIER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9888TNLGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28-VFQFP |
| IDT5V9888TNLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| IDT5V9888TPFGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9888TPFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9910A-2SOG | 功能描述:IC BUFFER ZD PLL SGL I/O 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ JR 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。