參數(shù)資料
型號(hào)： IDT5V9888PFGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 500 MHz, OTHER CLOCK GENERATOR, PQFP32
封裝： GREEN, TQFP-32
文件頁(yè)數(shù)： 18/37頁(yè)
文件大?。?/td> 354K
代理商： IDT5V9888PFGI8
25
INDUSTRIALTEMPERATURERANGE
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Standard JTAG Timing
NOTE:
t1 = tTCLKLOW
t2 = tTCLKHIGH
t3 = tTCLKFALL
t4 = tTCLKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
TCLK
TDI/TMS
TDO
TRST
tTCLK
t1
t2
t3
t4
t5
t6
tDS
tDH
tDO
TDO
JTAG
AC ELECTRICAL CHARACTERISTICS
NOTE:
1. Guaranteed by design.
SYSTEMINTERFACEPARAMETERS
Symbol
Parameter
Min.
Max.
Units
tDO
DataOutput(1)
—20
ns
tDOH
Data Output Hold(1)
0
—
ns
tDS
Data Input, tRISE = 3ns
10
—
ns
tDH
Data Input, tFALL = 3ns
10
—
ns
NOTE:
1. 50pF loading on external output signals.
Symbol
Parameter
Min.
Max.
Units
tTCLK
JTAG Clock Input Period
100
—
ns
tTCLKHIGH
JTAG Clock HIGH
40
—
ns
tTCLKLOW
JTAG Clock Low
40
—
ns
tTCLKRISE
JTAG Clock Rise Time
—
5(1)
ns
tTCLKFALL
JTAG Clock Fall Time
—
5(1)
ns
tRST
JTAG Reset
50
—
ns
tRSR
JTAG Reset Recovery
50
—
ns
Inorderforthesaveandrestoreinstructionstofunctionproperly,theIDT5V9888mustnotbeinshutdownmode(SHUTDOWNpinasserted). Intheevent
of an interrupt of some sort such as a power down of the part in the middle of a save or restore operation, the contents to or from the EEPROM will be partially
loaded, and a CRC error will be generated. The CERR bit (0x81) will be asserted to indicate that an error has occurred. The LOSS_LOCK signal will also
beasserted.
Onpower-upoftheIDT5V9888,anautomaticrestoreisperformedtoloadtheEEPROMcontentsintotheinternalprogrammingregisters. Theauto-restore
willnotfunctionproperlyifthedeviceisinshutdownmode(SHUTDOWNpinasserted). TheIDT5V9888willbereadytoacceptaprogramminginstructiononce
it acknowledges its 7-bit I2Caddress.
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