- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67712 > IDT5V9888PFGI8 (INTEGRATED DEVICE TECHNOLOGY INC) 500 MHz, OTHER CLOCK GENERATOR, PQFP32 PDF資料下載
參數(shù)資料
| 型號： | IDT5V9888PFGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 29/37頁 |
| 文件大小： | 354K |
| 代理商： | IDT5V9888PFGI8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
35
INDUSTRIALTEMPERATURERANGE
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
0x60
0
00000
00
0x61
0
00000
00
DITH0
X2_0
0x62
0
00000
00
0x63
0
00000
00
0x64
0
00000
00
0x65
0
00000
00
0x66
0
00000
00
0x67
0
00000
00
0x68
0
00000
00
0x69
0
00000
00
DITH1
X2_1
0x6A
0
00000
00
0x6B
0
00000
00
0x6C
0
00000
00
0x6D
0
00000
00
0x6E
0
00000
00
0x6F
0
00000
00
SD0[3:0][0]
SS_OFFSET1[5:0]
SD0[3:0][11]
SD0[3:0][1]
SD0[3:0][10]
SD0[3:0][3]
SD0[3:0][2]
SD0[3:0][5]
SD0[3:0][6]
SD1[3:0][3]
NSSC0[3:0]
TSSC0[3:0]
SD1[3:0][1]
TSSC1[3:0]
NSSC1[3:0]
SD1[3:0][10]
SD1[3:0][9]
SD1[3:0][2]
SD0[3:0][4]
SD1[3:0][7]
SD0[3:0][7]
SD0[3:0][9]
SS_OFFSET0[5:0]
SD1[3:0][0]
SD0[3:0][8]
SD1[3:0][4]
SD1[3:0][5]
SD1[3:0][8]
SD1[3:0][11]
SD1[3:0][6]
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
CERR
0x82
0x83
0x84
0x85
0x86
0x87
0x88
SPREAD SPRECTRUM SETTINGS FOR PLL0
SS_OFFSET0=SS Fractional Offset/ First Sample (Unsigned);
TSSC0=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);
NSSC0=# of SS Samples to Use from SS Memory (Default is "0");
DITH0=LSB DITHER on
Σ, ("1"=dither on, "0"=off (Default));
X2_0=
Σ output x2, ("1"=x2, "0"=normal (Default));
SD0=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET0, then SS_OFFSET0+SD0[0], etc. (Default is "0");
SPREAD SPRECTRUM SETTINGS FOR PLL1
SS_OFFSET1=SS Fractional Offset/ First Sample (Unsigned);
TSSC1=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);
NSSC1=# of SS Samples to Use from SS Memory (Default is "0");
DITH1=LSB DITHER on
Σ, ("1"=dither on, "0"=off (Default));
X2_1=
Σ output x2, ("1"=x2, "0"=off (Default));
SD1=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET1, then SS_OFFSET1+SD1[0], etc. (Default is "0");
CRC error in EEPROM
CERR = CRC error bit indicator ("1`" = CRC error)
Read-Only
RAM (PROGRAMMING REGISTER) TABLES
ADDR
765
43
210
Default
Register
Hex Value
7
6543
210
BIT #
(Default Settings)
DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| IDT5V9888PFGI | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| IDT5V9955BFGI | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA96 |
| IDT7216L20J8 | 16-BIT, DSP-MULTIPLIER, PQCC68 |
| IDT7216L25PQF | 16-BIT, DSP-MULTIPLIER, PQFP64 |
| IDT7216L45PQF | 16-BIT, DSP-MULTIPLIER, PQFP64 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9888TNLGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28-VFQFP |
| IDT5V9888TNLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| IDT5V9888TPFGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9888TPFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9910A-2SOG | 功能描述:IC BUFFER ZD PLL SGL I/O 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ JR 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復。