- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67712 > IDT5V9888PFGI8 (INTEGRATED DEVICE TECHNOLOGY INC) 500 MHz, OTHER CLOCK GENERATOR, PQFP32 PDF資料下載
參數(shù)資料
| 型號： | IDT5V9888PFGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 24/37頁 |
| 文件大?。?/td> | 354K |
| 代理商： | IDT5V9888PFGI8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
30
INDUSTRIALTEMPERATURERANGE
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
AC TIMING ELECTRICAL CHARACTERISTICS
(SPREAD SPECTRUM GENERATION = OFF)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max
Unit
fIN
InputFrequency
InputFrequencyLimit
1(1)
—
400
MHz
1/t1
OutputFrequency
SingleEndedClockoutputlimit(LVTTL)
0.0049
—
200
MHz
DifferentialClockoutputlimit(LVPECL/LVDS)
0.0049
—
500
fVCO
VCO Frequency
VCOoperatingFrequencyRange
10
—
1100
MHz
fPFD
PFD Frequency
PFDoperatingFrequencyRange
0.4(1)
—
400
MHz
fBW
LoopBandwidth
Basedonloopfilterresistorandcapacitorvalues
0.03
—
40
MHz
t2
Input Duty Cycle
Duty Cycle for Input
40
—
60
%
t3
Output Duty Cycle
Measured at VDD/2, FOUT
≤ 200MHz
45
—
55
%
Measured at VDD/2, FOUT > 200MHz
40
—
60
Slew Rate
Single-EndedOutputclockriseandfalltime,
—
2.75
—
SLEWx(bits) = 00
20% to 80% of VDD (Output Load = 15pf)
Slew Rate
Single-EndedOutputclockriseandfalltime,
—
2
—
t4(2)
SLEWx(bits) = 01
20% to 80% of VDD (Output Load = 15pf)
V/ns
Slew Rate
Single-EndedOutputclockriseandfalltime,
—
1.25
—
SLEWx(bits) = 10
20% to 80% of VDD (Output Load = 15pf)
Slew Rate
Single-EndedOutputclockriseandfalltime,
—
0.75
—
SLEWx(bits) = 11
20% to 80% of VDD (Output Load = 15pf)
RiseTimes
LVDS, 20% to 80%
—
850
—
t5
FallTimes
—850
—
ps
RiseTimes
LVPECL, 20% to 80%
—
500
—
FallTimes
—500
—
t6
Outputthree-stateTiming
Timeforoutputtoenterorleavethree-statemode
—
150 +
ns
after SHUTDOWN/OE switches
1/FOUTX
t7
Clock Jitter(3,7)
Peak-to-peakperiodjitter,
fPFD > 20MHz
—
150
ps
CLK outputs measured at VDD/2
fPFD < 20MHz
—
200
—
t8
Output Skew(8)
Skew between output to output on the same bank
—
150
ps
(bank 4 and bank 5 only)(4,5)
t9
LockTime
PLL Lock Time from Power-up(6)
—10
20
ms
t10
Locktime(9)
PLLLocktimefromshutdownmode
—
20
100
s
t11
Write-ProtectTime
WRITE ENABLE ↑ after tSAVE
10
—
ms
NOTES:
1. Practical lower input frequency is determined by loop filter settings.
2. A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.
3. Input frequency is the same as the output with all output banks running at the same frequency.
4. Skew measured between all output pairs under identical input and output interfaces, same PLL and PLL multiplication and post divider value, transitions and load conditions
on any one device.
5. Skew measured between the cross points of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
6. Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
7. Guaranteed by design but not production tested.
8. Outputs are aligned upon device power-on. If an output divider ratio is changed (via programming or Manual Frequency Control), then outputs are no longer guaranteed to
be synchronized.
9. Actual PLL lock time depends on the loop configuration.
SPREAD SPECTRUM GENERATION SPECIFICATIONS
Symbol
Parameter
Description
Min.
Typ.
Max
Unit
fIN
InputFrequency
InputFrequencyLimit
1(1)
—
400
MHz
fMOD
Mod Freq
ModulationFrequency
—
33
—
kHz
fSPREAD
SpreadValue
AmountofSpreadValue(Programmable)-DownSpread
-0.5, -1, -2.5, -3.5, -4
%fOUT
AmountofSpreadValue(Programmable)-CenterSpread
-0.5 to +0.5
NOTE:
1. Practical lower input frequency is determined by loop filter settings.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT5V9888PFGI | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| IDT5V9955BFGI | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA96 |
| IDT7216L20J8 | 16-BIT, DSP-MULTIPLIER, PQCC68 |
| IDT7216L25PQF | 16-BIT, DSP-MULTIPLIER, PQFP64 |
| IDT7216L45PQF | 16-BIT, DSP-MULTIPLIER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9888TNLGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28-VFQFP |
| IDT5V9888TNLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| IDT5V9888TPFGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9888TPFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9910A-2SOG | 功能描述:IC BUFFER ZD PLL SGL I/O 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ JR 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復。