- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67712 > IDT5V9888PFGI8 (INTEGRATED DEVICE TECHNOLOGY INC) 500 MHz, OTHER CLOCK GENERATOR, PQFP32 PDF資料下載
參數(shù)資料
| 型號： | IDT5V9888PFGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 35/37頁 |
| 文件大?。?/td> | 354K |
| 代理商： | IDT5V9888PFGI8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當前第35頁第36頁第37頁
7
INDUSTRIALTEMPERATURERANGE
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Feedback-Divider
N[11:0]andA[3:0]arethebitsusedtoprogramthefeedback-dividerforPLL0(N0andA0)andPLL1(N1andA1). Ifspreadspectrumgenerationisenabled
foreitherPLL0orPLL1,thenthe SS_OFFSET[5:0]bits(0x61,0x69)wouldbefactoredintotheoverallfeedbackdividervalue. SeetheSPREADSPECTRUM
GENERATIONsectionformoredetailsonhowtoconfigurePLL0andPLL1whenspreadspectrumisenabled. ThetwoPLLscanalsobeconfiguredforfractional
divideratios. SeeFRACTIONALDIVIDERformoredetails. ForPLL2,onlytheN[11:0]bits(N2)areusedtoprogramitsfeedbackdividerandthereisnospread
spectrum generation and fractional divides capability. The12-bit feedback-divider integer values range from 1 to 4095.
The following equations govern how the feedback divider value is set. Note that the equations are different for PLL0/PLL1 and PLL2
PLL0 and PLL1:
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] * 1/64
(Eq. 3)
M = 2*N[11:0] + A[3:0] + 1 (spread spectrum disabled)
(Eq. 4)
A[3:0] = 0000 = -1
= 0001 = 1
= 0010 = 2
= 0011 = 3
.
= 1111 = 15
Note: A[3:0] < (N[11:0] - 1), must be met when using A.
PLL2:
M = N[11:0]
(Eq. 5)
The user can achieve an even or odd integer divide ratio for both PLL0 and PLL1 by setting the A[3:0] bits accordingly and disabling the spread spectrum.
AfractionaldividecanalsobesetforPLL0andPLL1byusingtheA[3:0]bitsinconjunctionwiththeSS_OFFSET[5:0]bits,whichisdetailedintheFRACTIONAL
DIVIDERsection. NotethattheVCOhasafrequencyrangeof10MHzto1100MHz. To maintainlowjitter,itisbesttomaximizetheVCOfrequency. Forexample,
if the reference clock is 100MHz and a 200MHz clock is required, to achieve the best jitter performance, multiply the 100MHz by 11 to get the VCO running at
thehighestpossiblefrequencyof1100MHzandthendivideitdowntoget200MHz. Orifthereferenceclockis25MHzand20MHzistherequiredclock,multiply
the 25MHz by 40 to get the VCO running at 1000MHz and then divide it down to get 20MHz. If N is set to '0x00', the VCO will slew to the minimum frequency.
Post-Divider
Q[9:0] are the bits used to program the 10-bit post-dividers on output banks OUT2-6. OUT1 bank does not have a 10-bit post-divider or any other post-
divide along its path. The 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023.
There is the option to choose between disabling the post-divider, utilizing a div/1, a div/2, or the 10-bit post-divider by using the PM[1:0] bits. . Each bank,
except for OUT1, has a set of PM bits. When disabling the post-divider, no clock will appear at the outputs, but will remain powered on. The values are listed
in the table below.
PM[1:0]
P Post-Divider
00
disabled
01
div/1
10
div/2
11
Q[9:0] + 2 (Eq. 6)
00
01
10
11
/2
/ (Q+2)
PM[1:0]
/2
To Outputs
VCO
P
Post-Divider Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT5V9888PFGI | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| IDT5V9955BFGI | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA96 |
| IDT7216L20J8 | 16-BIT, DSP-MULTIPLIER, PQCC68 |
| IDT7216L25PQF | 16-BIT, DSP-MULTIPLIER, PQFP64 |
| IDT7216L45PQF | 16-BIT, DSP-MULTIPLIER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9888TNLGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28-VFQFP |
| IDT5V9888TNLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| IDT5V9888TPFGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9888TPFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9910A-2SOG | 功能描述:IC BUFFER ZD PLL SGL I/O 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ JR 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。