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參數(shù)資料
| 型號： | IDT5V9888PFGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 8/37頁 |
| 文件大?。?/td> | 354K |
| 代理商： | IDT5V9888PFGI8 |
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INDUSTRIALTEMPERATURERANGE
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Understanding the GIN Signals
Duringpowerup,thepartwillvirtuallybeinMFCmode2,therefore,thevaluesofGIN3,GIN2,GIN1andGIN0willbelatchedandusedforPLLconfiguration
selection,regardlessofthestateoftheI2C/JTAG pin. GIN4isnotlatched,andwillassumetheLOWstateinternallywheninprogrammingmode. Thismeans
that when in programming mode, the PLL configuration can only be changed by writing directly to the registers of the currently selected configuration. When
in MFC mode 2, configuration 0 or 1 (GIN4=0) should be selected if you do not want to change configurations when entering or leaving programming mode.
The GIN pins should be held LOW during power up to select configuration0 as default.
When not in programming mode, the GIN inputs directly control the selected configuration. The internal GINx signals can be individually disabled via
programmingtheGINENbits(0x06). WhendisabledbysettingGINENxto"0",theGINxinputsmaybeleftfloating,butduringpowerup,theGINpinswillstill
latch. Disabled inputs are interpreted as LOW by the internal state machines. Even if disabled, GIN2, GIN1, GIN0 and GIN3 pins will be enabled if required
forI2CorJTAGprogrammingfunctionswheninprogrammingmode. TheCLK_SELfunctionontheGIN4pinwillberenderedcompletelynon-functionalwhen
disabled.
SHUTDOWN/ENABLE OF OUTPUTS
TheSHUTDOWN/OEpin,alongwithinternalbits,controlstheenabling/disablingoftheoutputbanks. TheSHUTDOWN/OEpincanbeprogrammedtofunction
as an output enable or global shutdown. The polarity of the SHUTDOWN/OE signal pin can be programmed to be either active HIGH or LOW with the SP bit
(0x1C). When SP is "0", the pin becomes active HIGH and when SP is "1", the pin becomes active LOW. The SH bit(0x1C) determines the function of the
SHUTDOWN/OE signal pin. If SH is "1", the signal pin is SHUTDOWN and functions as a global shutdown. This will override the OEx (0x1C), OSx (0x1D),
and PLLSx (0x1E) bits. If SH is "0", the signal pin is OE and functions as an enable/disable of the output banks. If used as an output enable/disable, each
outputbankcanbeindividuallyprogrammedtobeenabledordisabledbytheOEpin.bysettingOExbitsto"1". IftheOEsignalpinisasserted,theoutputbanks
thathastheircorrespondingOExbitsetto"1"willbedisabled.TheOEMxbitsdeterminetheoutputs'disablestate. Whensetto"0x"theoutputswillbetristated.
When set to "10", the outputs will be pulled low. When set to "11", the outputs will be pulled high. Inverted outputs will be parked in the opposite state. If the
OExbitsaresetto"0",thestatesofthecorrespondingoutputbankswillnotbeimpactedbythestateoftheOEpin. Toindividuallyenable/disableviaprogramming
insteadoftheOEpin,hardwiretheOEpintoVddorGND(dependingifitisactiveHIGHorLOW)asiftodisabletheoutputs. ThentoggletheOExbitstoeither
"0" to enable or "1" to disable.
When the chip is in shutdown, the outputs, the reference oscillator, and the I2C /JTAG pin are powered down. The outputs will be tristated and the I2C
/JTAGpinwillbesettoMFCmode(MIDlevel). Programmingwillnotbeallowed. TheGINxpinsandclockinputsremainoperational. ThePLLisnotdisabled.
The SHUTDOWN pin must be reasserted in order to program the part or to resume operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9888TNLGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28-VFQFP |
| IDT5V9888TNLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| IDT5V9888TPFGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9888TPFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9910A-2SOG | 功能描述:IC BUFFER ZD PLL SGL I/O 24-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ JR 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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