參數(shù)資料
型號: IDT82V3355TFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 100/135頁
文件大?。?/td> 0K
描述: IC PLL WAN SYNC ETH 64-TQFP
標準包裝: 1,250
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 82V3355TFG8
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Programming Information
67
May 19, 2009
IN2_DIFF_CNFG - Differential Input Clock 2 Configuration
Address: 1AH
Type: Read / Write
Default Value: 00000011
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 1AH).
6LOCK_8K
This bit, together with the DIRECT_DIV bit (b7, 1AH), determines whether the DivN Divider or the Lock 8k Divider is used for
IN2_DIFF:
5 - 4
BUCKET_SEL[1:0]
These bits select one of the four groups of leaky bucket configuration registers for IN2_DIFF:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
3 - 0
IN_FREQ[3:0]
These bits set the DPLL required frequency for IN2_DIFF:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN2_DIFF, the required frequency should not be set higher than that of the input clock.
76
543
210
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
Both bypassed (default)
0
1
Lock 8k Divider
10
DivN Divider
11
Reserved
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