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| 型號(hào)： | IDT82V3355TFG8 |
| 廠(chǎng)商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 56/135頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN SYNC ETH 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,250 |
| 類(lèi)型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，PECL |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | 82V3355TFG8 |
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IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Functional Description
27
May 19, 2009
3.8.2.2
Non-Revertive Switch (T0 only)
In Non-Revertive switch, the T0 selected input clock is not switched
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the highest priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smallest ‘n’ is selected. See Table 9 for the ‘n’ assigned to
each input clock.
3.8.3
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
The
selected
input
clock
is
indicated
by
the
CURRENTLY_SELECTED_INPUT[3:0] bits. Note if the T4 selected
input clock is a T0 DPLL output, it can not be indicated by these bits.
The qualified input clocks with the three highest priorities are indi-
cated by HIGHEST_PRIORITY_VALIDATED[3:0] bits, the SECOND_
PRIORITY_VALIDATED[3:0]
bits
and
the
THIRD_PRIORITY
_VALIDATED[3:0] bits respectively. If more than one input clock has the
same priority, the input clock with the smallest ‘n’ is indicated by the
HIGHEST_PRIORITY_VALIDATED[3:0] bits. See Table 9 for the ‘n’
assigned to the input clock.
When the device is configured in Automatic selection and Revertive
switch
is
enabled,
the
input
clock
indicated
by
the
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi-
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
When all the input clocks for T4 path changes to be unqualified, the
INPUT_TO_T4 1 bit will be set. If the INPUT_TO_T4 2 bit is ‘1’, an inter-
rupt will be generated.
Table 15: Related Bit / Register in Chapter 3.8
Bit
Register
Address (Hex)
T0_FOR_T4
T4_INPUT_SEL_CNFG
51
INn_CMOS 1 (n = 1, 2 or 3) / INn_DIFF 1 (n = 1 or 2)
INPUT_VALID1_STS, INPUT_VALID2_STS
4A, 4B
INn_CMOS 2 (n = 1, 2 or 3) / INn_DIFF 2 (n = 1 or 2)
INTERRUPTS1_STS, INTERRUPTS2_STS
0D, 0E
INn_CMOS 3 (n = 1, 2 or 3) / INn_DIFF 3 (n = 1 or 2)
INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG
10, 11
INn_CMOS_NO_ACTIVITY_ALARM (n = 1, 2 or 3)
IN1_IN2_CMOS_STS, IN3_CMOS_STS
44, 47
INn_CMOS_FREQ_HARD_ALARM (n = 1, 2 or 3)
INn_CMOS_PH_LOCK_ALARM (
n = 1, 2 or 3)
INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2)
IN1_IN2_DIFF_STS
45
INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2)
INn_DIFF_PH_LOCK_ALARM (n = 1 or 2)
IN_NOISE_WINDOW
PHASE_MON_PBO_CNFG
78
ULTR_FAST_SW
MON_SW_PBO_CNFG
0B
LOS_FLAG_TO_TDO
T0_MAIN_REF_FAILED 1
INTERRUPTS2_STS
0E
T0_MAIN_REF_FAILED 2
INTERRUPTS2_ENABLE_CNFG
11
INPUT_TO_T4 1
INTERRUPTS3_STS
0F
INPUT_TO_T4 2
INTERRUPTS3_ENABLE_CNFG
12
REVERTIVE_MODE
INPUT_MODE_CNFG
09
INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3)
IN1_IN2_CMOS_SEL_PRIORITY_CNFG, IN3_CMOS_SEL_PRIORITY_CNFG
27 *, 2A *
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
28 *
CURRENTLY_SELECTED_INPUT[3:0]
PRIORITY_TABLE1_STS
4E *
HIGHEST_PRIORITY_VALIDATED[3:0]
SECOND_PRIORITY_VALIDATED[3:0]
PRIORITY_TABLE2_STS
4F *
THIRD_PRIORITY_VALIDATED[3:0]
T4_T0_SEL
T4_T0_REG_SEL_CNFG
07
Note: * The setting in the 27, 28, 2A, 4E and 4F registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
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