參數(shù)資料
型號(hào)： IDT82V3355TFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 42/135頁
文件大小： 0K
描述： IC PLL WAN SYNC ETH 64-TQFP
標(biāo)準(zhǔn)包裝： 1,250
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 3:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 82V3355TFG8
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Pin Description
14
May 19, 2009
IN2_POS
IN2_NEG
25
26
I
PECL/LVDS
IN2_POS / IN2_NEG: Positive / Negative Input Clock 2
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz or
622.08 MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL
or LVDS is automatically detected.
Single-ended input for differential input is also supported. Refer to Chapter 8.3.2.3 Single-
IN3_CMOS
34
I
pull-down
CMOS
IN3_CMOS: Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
Output Frame Synchronization Signal
FRSYNC_8K
17
O
CMOS
FRSYNC_8K: 8 kHz Frame Sync Output
An 8 kHz signal is output on this pin.
MFRSYNC_2K
18
O
CMOS
MFRSYNC_2K: 2 kHz Multiframe Sync Output
A 2 kHz signal is output on this pin.
Output Clock
OUT1_POS
OUT1_NEG
19
20
O
PECL/LVDS
OUT1_POS / OUT1_NEG: Positive / Negative Output Clock 1
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz, 125 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz, 312.5 MHz or
622.08 MHz clock is differentially output on this pair of pins.
OUT2
56
O
CMOS
OUT2: Output Clock 2
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz, 125 MHz, 155.52 MHz, 156.25 MHz or 312.5 MHz clock is output on
this pin.
Microprocessor Interface
CS
44
I
pull-up
CMOS
CS: Chip Selection
A transition from high to low must occur on this pin for each read or write operation and this
pin should remain low until the operation is over.
INT_REQ
5
O
CMOS
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
SDI
CLKE
43
42
I
pull-down
CMOS
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-
ally clocked into the device on the rising edge of SCLK.
CLKE: SCLK Active Edge Selection
In Serial mode, this pin selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
SDO
52
I/O
pull-down
CMOS
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
SCLK
47
I
pull-down
CMOS
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Type
Description 1
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