參數資料
型號: IDT82V3355TFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數: 119/135頁
文件大?。?/td> 0K
描述: IC PLL WAN SYNC ETH 64-TQFP
標準包裝: 1,250
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網,SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數: 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 82V3355TFG8
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Programming Information
84
May 19, 2009
IN3_CMOS_STS - CMOS Input Clock 3 Status
Address: 47H
Type: Read
Default Value: XXXXX110
Bit
Name
Description
7 - 3
-
Reserved.
2
IN3_CMOS_FREQ_HARD_ALARM
This bit indicates whether IN3_CMOS is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
1
IN3_CMOS_NO_ACTIVITY_ALARM
This bit indicates whether IN3_CMOS is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
0
IN3_CMOS_PH_LOCK_ALARM
This bit indicates whether IN3_CMOS is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
7
6
5
4
3
210
--
-
IN3_CMOS_FRE
Q_HARD_ALAR
M
IN3_CMOS_NO_
ACTIVITY_ALAR
M
IN3_CMOS_PH_
LOCK_ALARM
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